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Freescale Semiconductor
Technical Data
Document Number: MPC8360EEC Rev. 2, 12/2007
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications
This document provides an overview of the MPC8360E/58E PowerQUICCTM II Pro processor revision 2.x TBGA features, including a block diagram showing the major functional components. This device is a cost-effective, highly integrated communications processor that addresses the needs of the networking, wireless infrastructure and telecommunications markets. Target applications include next generation DSLAMs, network interface cards for 3G basestations (Node Bs), routers, media gateways and high end IADs. The device extends current PowerQUICC II Pro offerings, adding higher CPU performance, additional functionality, faster interfaces and robust interworking between protocols while addressing the requirements related to time-to-market, price, power, and package size. This device can be used for the control plane along with data plane functionality. For functional characteristics of the processor, refer to the MPC8360E Integrated Communications Processor Family Reference Manual, Rev. 2. To locate any published errata or updates for this document, contact your Freescale sales office.
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 UCC Ethernet Controller: Three-Speed Ethernet, MII Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 HDLC, BISYNC, Transparent, and Synchronous UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . 68 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 System Design Information . . . . . . . . . . . . . . . . . . . 104 Document Revision History. . . . . . . . . . . . . . . . . . . 108 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 108
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
Overview
1
Overview
This section describes a high-level overview including features and general operation of the MPC8360E/58E PowerQUICCTM II Pro processor. A major component of this device is the e300 core which includes 32 Kbytes of instruction and data cache and is fully compatible with the PowerPCTM 603e instruction set. The new QUICC EngineTM module provides termination, interworking, and switching between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine module's enhanced interworking eases the transition and reduces investment costs from ATM to IP based systems. The other major features include a dual DDR SDRAM memory controller for the MPC8360E, which allows equipment providers to partition system parameters and data in an extremely efficient way, such as using one 32-bit DDR memory controller for control plane processing and the other for data plane processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine.
e300 Core 32KB I-Cache 32KB D-Cache Security Engine System Interface Unit (SIU) Memory Controllers GPCM/UPM/SDRAM 32/64 DDR Interface Unit PCI Bridge Local Bus Bus Arbitration Multi-User RAM DUART Serial DMA & 2 Virtual DMAs Dual I2C 4 Channel DMA Interrupt Controller UCC1 UCC2 UCC3 UCC4 UCC5 UCC6 UCC7 UCC8 MCC SPI1 SPI2 USB Protection & Configuration System Reset Clock Synthesizer DDRC1 DDRC2 PCI Local
Classic G2 MMUs FPU JTAG/COP Power Management Timers
QUICC Engine Module Baud Rate Generators Parallel I/O Accelerators
Dual 32-bit RISC CP
Time Slot Assigner Serial Interface
8 TDM Ports
8 MII/ RMII
2 GMII/ RGMII/TBI/RTBI
2 UTOPIA/POS (124 MPHY)
Figure 1. MPC8360E Block Diagram
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 2 Freescale Semiconductor
Overview
e300 Core 32KB I-Cache 32KB D-Cache Security Engine
System Interface Unit (SIU) Memory Controllers GPCM/UPM/SDRAM 32/64 DDR Interface Unit PCI Bridge Local Bus Bus Arbitration DDRC PCI Local
Classic G2 MMUs FPU JTAG/COP Power Management Timers
QUICC Engine Module Baud Rate Generators Parallel I/O UCC1 UCC2 UCC3 UCC4 UCC5 UCC8 SPI1 SPI2 USB Accelerators Multi-User RAM Serial DMA & 2 Virtual DMAs
DUART Dual I2C 4 Channel DMA Interrupt Controller Protection & Configuration System Reset Clock Synthesizer
Dual 32-bit RISC CP
Time Slot Assigner Serial Interface
4 TDM Ports
6 MII/ RMII
2 GMII/ RGMII/TBI/RTBI
1 UTOPIA/POS (31/124 MPHY)
Figure 2. MPC8358E Block Diagram
Major features of the MPC8360E/58E are as follows: * e300 PowerPC processor core (enhanced version of the MPC603e core) -- Operates at up to 667 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E) -- High-performance, superscalar processor core -- Floating-point, integer, load/store, system register, and branch processing units -- 32-Kbyte instruction cache, 32-Kbyte data cache -- Lockable portion of L1 cache -- Dynamic power management -- Software-compatible with the Freescale processor families implementing the Power ArchitectureTM technology * QUICC Engine unit -- Two 32-bit RISC controllers for flexible support of the communications peripherals, each operating up to 500 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E) -- Serial DMA channel for receive and transmit on all serial channels
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Overview
-- QE peripheral request interface (for SEC, PCI, IEEE(R) Std 1588TM) -- Eight universal communication controllers (UCCs) on the MPC8360E and six UCCs on the MPC8358E supporting the following protocols and interfaces (not all of them simultaneously): - IEEE Std. 1588 protocol supported - 10/100 Mbps Ethernet/IEEE Std. 802.3(R) CDMA/CS interface through a media-independent interface (MII, RMII, RGMII)1 - 1000 Mbps Ethernet/IEEE Std. 802.3 CDMA/CS interface through a media-independent interface (GMII, RGMII, TBI, RTBI) on UCC1 and UCC2 - 9.6K jumbo frames - ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1 and AAL5 in accordance ITU-T I.363.5 - ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex (with 4 CPS packets per cell) in accordance ITU-T I.366.1 and I.363.2 - ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM forum TM4.1 for up to 64K simultaneous ATM channels - ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance with ITU-T I.163.1 and ATM Forum af-vtoa-00-0078.000 - IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in accordance with the ATM forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001 (Version 1.1) - ATM Transmission Convergence layer support in accordance with ITU-T I.432 - ATM OAM handling features compatible with ITU-T I.610 - PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the following RFCs: 1661, 1662, 1990, 2686 and 3153 - IP support for IPv4 packets including TOS, TTL and header checksum processing - Ethernet over first mile IEEE Std. 802.3ah(R) - Shim header - Ethernet-to-Ethernet/AAL5/AAL2 inter-working - L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q(R) VLAN tags - ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including bridging of ATM ports to Ethernet ports - Extensive support for ATM statistics and Ethernet RMON/MIB statistics - AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate - Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY - POS hardware; microcode must be loaded as an IRAM package - Transparent up to 70-Mbps full-duplex - HDLC up to 70-Mbps full-duplex - HDLC BUS up to 10 Mbps
1. SMII or SGMII media-independent interface is not currently supported
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Overview
*
- Asynchronous HDLC - UART - BISYNC up to 2 Mbps - User-programmable Virtual FIFO size - QUICC Multichannel Controller (QMC) for 64 TDM channels -- One multichannel communication controller (MCC) only on the MPC8360E supporting the following: - 256 HDLC or transparent channels - 128 SS7 channels - Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces -- Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional 2*128 MultiPHY with extended address) and one UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY -- Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management -- Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3 rates in clear channel -- Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC and MCC serial channels (MCC is only available on the MPC8360E) -- Four independent 16-bit timers that can be interconnected as four 32-bit timers -- Interworking functionality: - Layer 2 10/100-Base T Ethernet switch - ATM-to-ATM switching (AAL0, 2, 5) - Ethernet-to-ATM switching with L3/L4 support - PPP interworking Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, 802.11i, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs). -- Public key execution unit (PKEU) supporting the following: - RSA and Diffie-Hellman - Programmable field size up to 2048 bits - Elliptic curve cryptography - F2m and F(p) modes - Programmable field size up to 511 bits -- Data encryption standard execution unit (DEU) - DES, 3DES - Two key (K1, K2) or three key (K1, K2, K3) - ECB and CBC modes for both DES and 3DES -- Advanced encryption standard unit (AESU)
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Overview
*
-- Implements the Rinjdael symmetric key cipher -- Key lengths of 128, 192, and 256 bits, two key - ECB, CBC, CCM, and counter modes -- ARC four execution unit (AFEU) - Implements a stream cipher compatible with the RC4 algorithm - 40- to 128-bit programmable key -- Message digest execution unit (MDEU) - SHA with 160-, 224-, or 256-bit message digest - MD5 with 128-bit message digest - HMAC with either SHA or MD5 algorithm -- Random number generator (RNG) -- Four crypto-channels, each supporting multi-command descriptor chains - Static and/or dynamic assignment of crypto-execution units via an integrated controller - Buffer size of 256 bytes for each execution unit, with flow control for large data sizes -- Storage/NAS XOR parity generation accelerator for RAID applications Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory controller on the MPC8358E -- Programmable timing supporting both DDR1 and DDR2 SDRAM -- On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus; on the MPC8358E, the DDR bus can be configured as a 32-bit or a 64-bit bus -- 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the MPC8358E) data rate -- Four banks of memory, each up to 1 Gbyte -- DRAM chip configurations from 64 Mbits to 1 Gigabit with x8/x16 data ports -- Full ECC support (when the MPC8360E is configured as 2x32 bit DDR memory controllers, both support ECC) -- Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open pages for DDR2) -- Contiguous or discontiguous memory mapping -- Read-modify-write support -- Sleep mode support for self refresh SDRAM -- Supports auto refreshing -- Supports source clock mode -- On-the-fly power management using CKE -- Registered DIMM support -- 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2 -- External driver impedance calibration -- On-die termination (ODT)
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Overview
*
*
*
PCI interface -- PCI Specification Revision 2.3 compatible -- Data bus widths: - Single 32-bit data PCI interface that operates at up to 66 MHz -- PCI 3.3-V compatible (not 5-V compatible) -- PCI host bridge capabilities on both interfaces -- PCI agent mode supported on PCI interface -- Support for PCI-to-memory and memory-to-PCI streaming -- Memory prefetching of PCI read accesses and support for delayed read transactions -- Support for posting of processor-to-PCI and PCI-to-memory writes -- On-chip arbitration, supporting five masters on PCI -- Support for accesses to all PCI address spaces -- Parity support -- Selectable hardware-enforced coherency -- Address translation units for address mapping between host and peripheral -- Dual address cycle supported when the device is the target -- Internal configuration registers accessible from PCI Local bus controller (LBC) -- Multiplexed 32-bit address and data operating at up to 133 MHz -- Eight chip selects support eight external slaves -- Up to eight-beat burst transfers -- 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller -- Three protocol engines available on a per chip select basis: - General-purpose chip select machine (GPCM) - Three user programmable machines (UPMs) - Dedicated single data rate SDRAM controller -- Parity support -- Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit) Programmable interrupt controller (PIC) -- Functional and programming compatibility with the MPC8260 interrupt controller -- Support for 8 external and 35 internal discrete interrupt sources -- Support for one external (optional) and seven internal machine checkstop interrupt sources -- Programmable highest priority request -- Four groups of interrupts with programmable priority -- External and internal interrupts directed to communication processor -- Redirects interrupts to external INTA pin when in core disable mode -- Unique vector number for each interrupt source
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 7
Electrical Characteristics
*
*
*
*
* *
Dual industry-standard I2C interfaces -- Two-wire interface -- Multiple master support -- Master or slave I2C mode support -- On-chip digital filtering rejects spikes on the bus -- System initialization data is optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware DMA controller -- Four independent virtual channels -- Concurrent execution across multiple channels with programmable bandwidth control -- All channels accessible by local core and remote PCI masters -- Misaligned transfer capability -- Data chaining and direct mode -- Interrupt on completed segment and chain -- DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3]. There is one set for each DMA channel. The pins are multiplexed to the parallel IO pins with other QE functions. DUART -- Two 4-wire interfaces (RxD, TxD, RTS, CTS) -- Programming model compatible with the original 16450 UART and the PC16550D System timers -- Periodic interrupt timer -- Real-time clock -- Software watchdog timer -- Eight general-purpose timers IEEE Std. 1149.1TM compliant, JTAG boundary scan Integrated PCI bus and SDRAM clock generation
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8360E/58E. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.
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Electrical Characteristics
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings1
Characteristic Symbol VDD -0.3 to 1.32 -0.3 to 1.37 AV DD -0.3 to 1.32 -0.3 to 1.37 GVDD DDR DDR2 -0.3 to 2.75 -0.3 to 1.89 LVDD OVDD MVIN MVREF LVIN OVIN -0.3 to 3.63 -0.3 to 3.63 -0.3 to (GVDD + 0.3) -0.3 to (GVDD + 0.3) -0.3 to (LVDD + 0.3) -0.3 to (OV DD + 0.3) V V V V V V 2, 5 2, 5 4, 5 3, 5 V V Max Value Unit V Notes
Table 1 provides the absolute maximum ratings.
Core supply voltage For QE frequencies <500 MHz and e300 frequencies <667 MHz For a QE frequency of 500 MHz or an e300 frequency of 667 MHz PLL supply voltage For QE frequencies <500 MHz and e300 frequencies <667 MHz For a QE frequency of 500 MHz or an e300 frequency of 667 MHz DDR and DDR2 DRAM I/O voltage
Three-speed Ethernet I/O, MII management voltage PCI, local bus, DUART, system control and power management, I2C, SPI, and JTAG I/O voltage Input voltage DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals Local bus, DUART, CLKIN, system control and power management, I2C, SPI, and JTAG signals PCI Storage temperature range
OVIN TSTG
-0.3 to (OV DD + 0.3) -55 to 150
V C
6
Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3. 6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 4.
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Electrical Characteristics
2.1.2
Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the device. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Characteristic Core supply voltage For QE frequencies <500 MHz and e300 frequencies <667 MHz For a QE frequency of 500 MHz or an e300 frequency of 667 MHz PLL supply voltage For QE frequencies <500 MHz and e300 frequencies <667 MHz For a QE frequency of 500 MHz or an e300 frequency of 667 MHz DDR and DDR2 DRAM I/O supply voltage DDR DDR2 Three-speed Ethernet I/O supply voltage Three-speed Ethernet I/O supply voltage Three-speed Ethernet I/O supply voltage PCI, local bus, DUART, system control and power management, I2C, SPI, and JTAG I/O voltage Junction temperature LVDD0 LVDD1 LVDD2 OVDD TJ Symbol VDD 1.2 V 60 mV 1.3 V 50 mV AVDD 1.2 V 60 mV 1.3 V 50 mV GVDD 2.5 V 125 mV 1.8V 90 mV 3.3 V 330 mV 2.5 V 125 mV 3.3 V 330 mV 2.5 V 125 mV 3.3 V 330 mV 2.5 V 125 mV 3.3 V 330 mV 0 to 105 V V V V C 2 V V 1 Recommended Value Unit V Notes 1
Notes: 1. GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction--either in the positive or negative direction. 2. .The operating conditions for junction temperature, TJ, on the 600/333/400 MHz and 500/333/500 MHz on rev2.0 silicon is 0 C to 70 C. Please refer to General9 in the device errata document.
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Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltages at the interfaces of the device.
G/L/OVDD + 20% G/L/OVDD + 5% VIH G/L/OVDD
GND GND - 0.3 V VIL GND - 0.7 V Not to Exceed 10% of tinterface1
Note: 1. Note that tinterface refers to the clock period associated with the bus clock interface.
Figure 3. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
Figure 4 shows the undershoot and overshoot voltage of the PCI interface of the device for the 3.3-V signals, respectively.
11 ns (Min) +7.1 V Overvoltage Waveform 0V 4 ns (Max) 62.5 ns +3.6 V Undervoltage Waveform -3.5 V 7.1 V p-to-p (Min) 7.1 V p-to-p (Min)
4 ns (Max)
Figure 4. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
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Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
Table 3. Output Drive Capability
Driver Type Local bus interface utilities signals PCI signals PCI output clocks (including PCI_SYNC_OUT) DDR signal DDR2 signal 10/100/1000 Ethernet signals DUART, system control, GPIO signals
1
Output Impedance () 42 25 42 20 36 (half strength mode) 1 18 36 (half strength mode) 1 42 42 42
Supply Voltage OVDD = 3.3 V
GVDD = 2.5 V GVDD = 1.8 V LV DD = 2.5/3.3 V OVDD = 3.3 V OVDD = 3.3 V LV DD = 2.5/3.3 V
I2C,
SPI, JTAG
DDR output impedance values for half strength mode are verified by design and not tested
2.2
Power Sequencing
This section details the power sequencing considerations for the MPC8360E/58E.
2.2.1
Power-Up Sequencing
MPC8360E/58E does not require the core supply voltage (VDD and AVDD) and I/O supply voltages (GVDD, LVDD, and OVDD) to be applied in any particular order. During the power ramp up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of time that all input and output pins will actively be driven and cause contention and excessive current. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power
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Power Characteristics
supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 5.
Figure 5. Power Sequencing Example
Voltage I/O Voltage (GVDD, LV DD, OVDD)
Core Voltage (VDD, AVDD)
0.7 V 90% Time
I/O voltage supplies (GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one another.
2.2.2
Power-Down Sequencing
The MPC8360E/58E does not require the core supply voltage and I/O supply voltages to be powered-down in any particular order.
3
Power Characteristics
Table 4. MPC8360E TBGA Core Power Dissipation1
Core Frequency (MHz) 266 400 533 667 500 CSB QUICC Engine Frequency (MHz) Frequency (MHz) 266 266 266 333 333 500 400 400 400 500 Typical 5.0 4.5 4.8 5.8 5.9 Maximum 5.6 5.0 5.3 6.3 6.4 Unit W W W W W Notes 2, 3, 5 2, 3, 4 2, 3, 4 3, 6, 7, 8 3, 6, 7, 8
The estimated typical power dissipation values are shown in Table 4 and Table 5.
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Power Characteristics
Table 4. MPC8360E TBGA Core Power Dissipation1 (continued)
Core Frequency (MHz) 667 CSB QUICC Engine Frequency (MHz) Frequency (MHz) 333 500 Typical 6.1 Maximum 6.8 Unit W Notes 2, 3, 5, 9
Notes: 1. The values do not include I/O supply power (OVDD, LV DD, GVDD) or AVDD. For I/O power values, see Table 6. 2. Typical power is based on a voltage of VDD = 1.2 V or 1.3 V, a junction temperature of TJ = 105C, and a Dhrystone benchmark application. 3. Thermal solutions will likely need to design to a value higher than typical power on the end application, TA target, and I/O power. 4. Maximum power is based on a voltage of VDD = 1.2 V, WC process, a junction TJ = 105C, and an artificial smoke test. 5. Maximum power is based on a voltage of V DD = 1.3 V for applications that use 667MHz(CPU)/500(QE) with WC process, a junction TJ = 105C, and an artificial smoke test. 6. Typical power is based on a voltage of VDD = 1.3 V, a junction temperature of TJ = 70C, and a Dhrystone benchmark application. 7. Maximum power is based on a voltage of VDD = 1.3 V for applications that use 667MHz(CPU) or 500(QE) with WC process, a junction TJ = 70C, and an artificial smoke test. 8. This frequency combination is only available for rev2.0 silicon. 9. This frequency combination is not available for rev2.0 silicon.
Table 5. MPC8358E TBGA Core Power Dissipation1
Core Frequency (MHz) 266 400 CSB QUICC Engine Frequency (MHz) Frequency (MHz) 266 266 300 400 Typical 4.1 4.5 Maximum 4.5 5.0 Unit W W Notes 2, 3, 4 2, 3, 4
Notes: 1. The values do not include I/O supply power (OV DD, LV DD, GVDD) or AVDD. For I/O power values, see Table 6. 2. Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of TJ = 105C, and a Dhrystone benchmark application. 3. Thermal solutions will likely need to design to a value higher than typical power on the end application, TA target, and I/O power. 4. Maximum power is based on a voltage of VDD = 1.2 V, WC process, a junction TJ = 105C, and an artificial smoke test.
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Clock Input Timing
Table 6 shows the estimated typical I/O power dissipation for the device.
Table 6. Estimated Typical I/O Power Dissipation
Interface DDR I/O 65% utilization Rs = 20 Rt = 50 2 pairs of clocks Parameter 200 MHz, 1x32 bits 200 MHz, 1x64 bits 200 MHz, 2x32 bits 266 MHz, 1x32 bits 266 MHz, 1x64 bits 266 MHz, 2x32 bits 333 MHz, 1x32 bits 333 MHz, 1x64 bits 333 MHz, 2x32 bits Local Bus I/O Load = 25 pf 3 pairs of clocks 133 MHz, 32 bits 83 MHz, 32 bits 66 MHz, 32 bits 50 MHz, 32 bits PCI I/O Load = 30 pf 10/100/1000 Ethernet I/O Load = 20 pf Other I/O 33 MHz, 32 bits 66 MHz, 32 bits MII or RMII GMII or TBI RGMII or RTBI 0.1 GVDD (1.8 V) 0.3 0.4 0.6 0.35 0.46 0.7 0.4 0.53 0.81 GVDD (2.5 V) 0.46 0.58 0.92 0.56 0.7 1.11 0.65 0.82 1.3 0.22 0.14 0.12 0.09 0.05 0.07 0.01 0.04 0.04 OVDD (3.3 V) LV DD (3.3 V) LV DD Unit (2.5 V) W W W W W W W W W W W W W W W W W W W Multiply by number of interfaces used. Comments
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8360E/58E.
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RESET Initialization
4.1
DC Electrical Characteristics
Table 7. CLKIN DC Electrical Characteristics
Parameter Condition -- -- 0 V VIN OVDD 0 V VIN 0.5V or OV DD - 0.5V VIN OVDD 0.5 V VIN OVDD - 0.5 V Symbol VIH VIL IIN IIN IIN Min 2.7 -0.3 -- -- -- Max OVDD + 0.3 0.4 10 10 100 Unit V V A A A
Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device.
Input high voltage Input low voltage CLKIN input current PCI_SYNC_IN input current PCI_SYNC_IN input current
4.2
AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Table 8 provides the clock input (CLKIN/PCI_CLK) AC timing specifications for the device.
Table 8. CLKIN AC Timing Specifications
Parameter/Condition CLKIN/PCI_CLK frequency CLKIN/PCI_CLK cycle time CLKIN/PCI_CLK rise and fall time CLKIN/PCI_CLK duty cycle CLKIN/PCI_CLK jitter Symbol fCLKIN tCLKIN tKH, tKL tKHK/tCLKIN -- Min -- 15 0.6 40 -- Typical -- -- 1.0 -- -- Max 66.67 -- 2.3 60 150 Unit MHz ns ns % ps Notes 1 -- 2 3 4, 5
Notes: 1. Caution: The system, core, USB, security, and 10/100/1000 Ethernet must not exceed their respective maximum or minimum operating frequencies. 2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter--short term and long term--and is guaranteed by design. 5. The CLKIN/PCI_CLK driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8360E/58E.
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RESET Initialization
5.1
RESET DC Electrical Characteristics
Table 9. RESET Pins DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min 2.0 -0.3 Max OVDD + 0.3 0.8 10 -- 0.5 0.4 Unit V V A V V V
Table 9 provides the DC electrical characteristics for the RESET pins of the device.
Notes: 1. This table applies for pins PORESET, HRESET, SRESET and QUIESCE. 2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
5.2
RESET AC Electrical Characteristics
This section describes the AC electrical specifications for the reset initialization timing requirements of the device. Table 10 provides the reset initialization AC timing specifications for the DDR SDRAM component(s).
Table 10. RESET Initialization Timing Specifications
Parameter/Condition Required assertion time of HRESET or SRESET (input) to activate reset flow Required assertion time of PORESET with stable clock applied to CLKIN when the device is in PCI host mode Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN when the device is in PCI agent mode HRESET/SRESET assertion (output) HRESET negation to SRESET negation (output) Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the device is in PCI host mode Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the device is in PCI agent mode Input hold time for POR config signals with respect to negation of HRESET Min 32 32 Max -- -- Unit tPCI_SYNC_IN tCLKIN Notes 1 2
32
--
tPCI_SYNC_IN
1
512 16 4
-- -- --
tPCI_SYNC_IN tPCI_SYNC_IN tCLKIN
1 1 2
4
--
tPCI_SYNC_IN
1
0
--
ns
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RESET Initialization
Table 10. RESET Initialization Timing Specifications (continued)
Time for the device to turn off POR config signals with respect to the assertion of HRESET Time for the device to turn on POR config signals with respect to the negation of HRESET -- 1 4 -- ns tPCI_SYNC_IN 3 1, 3
Notes: 1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more details. 2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more details. 3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 11 provides the PLL and DLL lock times.
Table 11. PLL and DLL Lock Times
Parameter/Condition PLL lock times DLL lock times Min -- 7680 Max 100 122,880 Unit s csb_clk cycles 1, 2 Notes
Notes: 1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 22, "Clocking," for more information.
5.3
QE Operating Frequency Limitations
This section specify the limits of the AC electrical characteristics for the operation of the QE's communication interfaces.
NOTE
The settings listed below are required for correct hardware interface operation. Each protocol by itself requires a minimal QE operating frequency setting for meeting the performance target. Because the performance is a complex function of all the QE settings, the user should make use of the QE performance utility tool provided by Freescale to validate their system. Table 12 lists the maximal QE I/O frequencies and the minimal QE core frequency for each interface.
Table 12. QE Operating Frequency Limitations
Interface Ethernet Management: MDC/MDIO MII Interface Operating Frequency (MHz) 10 (max) 25 (typ) Max interface Bit Rate (Mbps) 10 100 Min QE Operating Frequency1 (MHz) 20 50 Notes
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DDR and DDR2 SDRAM
Table 12. QE Operating Frequency Limitations (continued)
Interface RMII GMII/RGMII/TBI/RTBI SPI (master/slave) UCC through TDM MCC UTOPIA L2 POS-PHY L2 HDLC Bus HDLC/Transparent UART/Async HDLC BISYNC USB Interface Operating Frequency (MHz) 50 (typ) 125 (typ) 10 (max) 50 (max) 25 (max) 50 (max) 50 (max) 10 (max) 50 (max) 3.68 (max internal ref clock) 2 (max) 48 (ref clock) Max interface Bit Rate (Mbps) 100 1000 10 70 16.67 800 800 10 50 115 (Kbps) 2 12 Min QE Operating Frequency1 (MHz) 50 250 20 8xF 16 x F 2xF 2xF 20 8/3 x F 20 20 96 2, 3 2 2, 4 2 2 Notes
Note: 1. The QE needs to run at a frequency higher than or equal to what is listed in this table. 2. `F' is the actual interface operating frequency. 3. The bit rate limit is independent of the data bus width (i.e. the same for serial, nibble, or octal interfaces). 4. TDM in high-speed mode for serial data interface.
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface of the MPC8360E/58E.
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
Table 13 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the device when GVDD(typ) = 1.8 V.
Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Symbol GVDD MVREF VTT VIH VIL Min 1.71 0.49 x GVDD MVREF - 0.04 MVREF + 0.125 -0.3 Max 1.89 0.51 x GV DD MVREF + 0.04 GVDD + 0.3 MVREF - 0.125 Unit V V V V V Notes 1 2 3
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DDR and DDR2 SDRAM
Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)
Output leakage current Output high current (VOUT = 1.420 V) Output low current (VOUT = 0.280 V) MV REF input leakage current Input current (0 V VIN OVDD) IOZ IOH IOL IVREF IIN -- -13.4 13.4 -- -- 10 10 -- -- 10 A mA mA A A 4
Notes: 1. GV DD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MV REF is expected to equal 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF cannot exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal MV REF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT GV DD.
Table 14 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 14. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V
Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1
Note: 1. This parameter is sampled. GVDD = 1.8 V 0.090 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 15 provides the recommended operating conditions for the DDR SDRAM component(s) of the device when GVDD(typ) = 2.5 V.
Table 15. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V
Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.95 V) Output low current (VOUT = 0.35 V) MV REF input leakage current Symbol GVDD MVREF VTT VIH VIL IOZ IOH IOL IVREF Min 2.375 0.49 x GVDD MVREF - 0.04 MVREF + 0.18 -0.3 -- -15.2 15.2 -- Max 2.625 0.51 x GVDD MVREF + 0.04 GVDD + 0.3 MVREF - 0.18 10 -- -- 10 Unit V V V V V A mA mA A 4 Notes 1 2 3
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Table 15. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V (continued)
Input current (0 V VIN OVDD) IIN -- 10 A
Notes: 1. GV DD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MV REF is expected to be equal to 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT GV DD.
Table 16 provides the DDR capacitance when GVDD(typ) = 2.5 V.
Table 16. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V
Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1
Note: 1. This parameter is sampled. GVDD = 2.5 V 0.125 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak to peak) = 0.2 V.
6.2
DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.
6.2.1
DDR and DDR2 SDRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR2 SDRAM interface when GVDD(typ) = 1.8 V.
Table 17. DDR2 SDRAM Input AC Timing Specifications for GVDD(typ) = 1.8 V
At recommended operating conditions with GVDD of 1.8 V 5%.
Parameter AC input low voltage AC input high voltage
Symbol VIL VIH
Min -- MVREF + 0.25
Max MVREF - 0.25 --
Unit V V
Notes
Table 18 provides the input AC timing specifications for the DDR SDRAM interface when GVDD(typ) = 2.5 V.
Table 18. DDR SDRAM Input AC Timing Specifications Mode for GVDD(typ) = 2.5 V
At recommended operating conditions with GVDD of 2.5 V 5%.
Parameter AC input low voltage
Symbol VIL
Min --
Max MVREF - 0.31
Unit V
Notes
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DDR and DDR2 SDRAM
Table 18. DDR SDRAM Input AC Timing Specifications Mode for GVDD(typ) = 2.5 V (continued)
At recommended operating conditions with GVDD of 2.5 V 5%.
AC input high voltage
VIH
MVREF + 0.31
--
V
Notes: 1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 n 7) or ECC (MECC[{0...7}] if n = 8).
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications Mode for GVDD(typ) = 2.5 V
At recommended operating conditions with GVDD of 2.5 V 5%.
Parameter MDQS--MDQ/MECC input skew per byte 333 MHz 266 MHz 200 MHz
Symbol tDISKEW
Min
Max
Unit ps
Notes 1, 2
-750 -1125 -1250
750 1125 1250
Notes: 1. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency. 2. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 n 7) or ECC (MECC[{0...7}] if n = 8).
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20 and Table 21 provide the output AC timing specifications and measurement conditions for the DDR and DDR2 SDRAM interface.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Source Synchronous Mode
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) 5%.
Parameter 8 MCK[n] cycle time, (MCK[n]/MCK[n] crossing) Skew between any MCK to ADDR/CMD 333 MHz 266 MHz 200 MHz ADDR/CMD output setup with respect to MCK 333 MHz 266 MHz 200 MHz ADDR/CMD output hold with respect to MCK 333 MHz 266 MHz - DDR1 266 MHz - DDR2 200 MHz MCS(n) output setup with respect to MCK 333 MHz 266 MHz 200 MHz
Symbol 1 tMCK tAOSKEW
Min 6 -1.0 -1.1 -1.2
Max 10 0.2 0.3 0.4 --
Unit ns ns
Notes 2 3
tDDKHAS 2.1 2.8 3.5 tDDKHAX 2.0 2.72.8 3.5
ns
4
--
ns
4
tDDKHCS 2.1 2.8 3.5
--
ns
4
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DDR and DDR2 SDRAM
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)
Parameter 8 MCS(n) output hold with respect to MCK 333 MHz 266 MHz 200 MHz MCK to MDQS MDQ/MECC/MDM output setup with respect to MDQS 333 MHz 266 MHz 200 MHz MDQ/MECC/MDM output hold with respect to MDQS 333 MHz 266 MHz 200 MHz MDQS preamble start MDQS epilogue end tDDKHMH tDDKHDS, tDDKLDS Symbol 1 tDDKHCX 2.0 2.7 3.5 -0.8 0.7 1.0 1.2 -- 0.7 1.0 1.2 -0.5 x tMCK - 0.6 -0.6 -0.5 x tMCK + 0.6 0.9 ns ns 7 7 ns 6 0.7 -- ns ns 5, 9 6 Min Max -- Unit ns Notes 4
tDDKHDX, tDDKLDX
tDDKHMP tDDKHME
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V. 3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock Control Register. For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set to align the address/command valid with the rising edge of MCK. 4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied cycle. 5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for a description and understanding of the timing modifications enabled by use of these bits. 6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device. 7. All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that tDDKHMP follows the symbol conventions described in note 1. 8. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency. 9. In rev2.0 silicon, tDDKHMH maximum meets the specification of 0.6ns. In rev 2.0 silicon, due to errata, tDDKHMH minimum is -0.9 ns. Please refer to DDR18 in the device errata document.
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DDR and DDR2 SDRAM
Figure 6 shows the DDR SDRAM output timing for address skew with respect to any MCK.
MCK[n] MCK[n] tMCK tAOSKEW(max)
ADDR/CMD
CMD tAOSKEW(min)
NOOP
ADDR/CMD
CMD
NOOP
Figure 6. Timing Diagram for tAOSKEW Measurement
Figure 7 provides the AC test load for the DDR bus.
Output Z0 = 50 RL = 50 GVDD/2
Figure 7. DDR AC Test Load Table 21. DDR and DDR2 SDRAM Measurement Conditions
Symbol VTH VOUT DDR MVREF 0.31 V 0.5 x GVDD DDR2 MVREF 0.25 V 0.5 x GVDD Unit V V Notes 1 2
Notes: 1. Data input threshold measurement point. 2. Data output measurement point.
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DDR and DDR2 SDRAM
Figure 8 shows the DDR SDRAM output timing diagram for source synchronous mode.
MCK[n] MCK[n] tMCK tDDKHAS ,tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP
Figure 8. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
Table 22 provides approximate delay information that can be expected for the address and command signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL. These numbers are the result of simulations for one topology. The delay numbers will strongly depend on the topology used. These delay numbers show the total delay for the address and command to arrive at the DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM.
Table 22. Expected Delays for Address/Command
Load 4 devices (12 pF) 9 devices (27 pF) 36 devices (108 pF) + 40 pF compensation capacitor 36 devices (108 pF) + 80 pF compensation capacitor Delay 3.0 3.6 5.0 5.2 Unit ns ns ns ns
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DUART
7
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the MPC8360E/58E.
7.1
DUART DC Electrical Characteristics
Table 23. DUART DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage OVDD High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A Input current (0 V VIN OV DD) Symbol VIH VIL VOH VOL IIN Min 2 -0.3 OV DD - 0.4 -- -- Max OVDD + 0.3 0.8 -- 0.2 10 Unit V V V V A 1 Notes
Table 23 provides the DC electrical characteristics for the DUART interface of the device.
Note: 1. Note that the symbol VIN, in this case, represents the OV IN symbol referenced in Table 1 and Table 2.
7.2
DUART AC Electrical Specifications
Table 24. DUART AC Timing Specifications
Parameter Minimum baud rate Maximum baud rate Oversample rate Value 256 > 1,000,000 16 Unit baud baud -- 1 2 Notes
Table 24 provides the AC timing parameters for the DUART interface of the device.
Notes: 1. Actual attainable baud rate will be limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample.
8
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management.
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.1
Three-Speed Ethernet Controller (10/100/1000 Mbps)-- GMII/MII/RMII/TBI/RGMII/RTBI Electrical Characteristics
The electrical characteristics specified here apply to all GMII (gigabit media independent interface), MII (media independent interface), RMII (reduced media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and MDC (management data clock). The MII, RMII, GMII and TBI interfaces are only defined for 3.3V, while the RGMII and RTBI interfaces are only defined for 2.5 V. The RGMII and RTBI interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer Device Specification Version 1.2a (9/22/2000). The electrical characteristics for the MDIO and MDC are specified in Section 8.3, "Ethernet Management Interface Electrical Characteristics."
8.1.1
10/100/1000 Ethernet DC Electrical Characteristics
All GMII, MII, RMII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes specified in Table 25 and Table 26. The potential applied to the input of a GMII, MII, RMII, TBI, RGMII, or RTBI receiver may exceed the potential of the receiver's power supply (i.e., a RGMII driver powered from a 3.6-V supply driving VOH into a RGMII receiver powered from a 2.5 V supply). Tolerance for dissimilar RGMII driver and receiver supply potentials is implicit in these specifications. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 25. RGMII/RTBI, GMII, TBI, MII, and RMII DC Electrical Characteristics (when operating at 3.3 V)
Parameter Supply voltage 3.3 V Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol LVDD VOH VOL VIH VIL IIN IOH = -4.0 mA IOL = 4.0 mA -- -- 0 V VIN LVDD Conditions -- LVDD = Min LVDD = Min -- -- Min 2.97 2.40 GND 2.0 -0.3 -- Max 3.63 LVDD + 0.3 0.50 LVDD + 0.3 0.90 10 Unit V V V V V A Notes 1
Note: 1. GMII/MII pins that are not needed for RGMII, RMII or RTBI operation are powered by the OVDD supply.
Table 26. RGMII/RTBI DC Electrical Characteristics (when operating at 2.5 V)
Parameters Supply voltage 2.5 V Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol LVDD VOH VOL VIH VIL IIN IOH = -1.0 mA IOL = 1.0 mA -- -- Conditions -- LVDD = Min LVDD = Min LVDD = Min LVDD = Min Min 2.37 2.00 GND - 0.3 1.7 -0.3 -- Max 2.63 LVDD + 0.3 0.40 LVDD + 0.3 0.70 10 Unit V V V V V A
0 V VIN LVDD
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.2
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.
8.2.1
GMII Timing Specifications
This sections describe the GMII transmit and receive AC timing specifications.
8.2.1.1
GMII Transmit AC Timing Specifications
Table 27. GMII Transmit AC Timing Specifications
Table 27 provides the GMII transmit AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK clock rise time, VIL(min) to VIH(max) GTX_CLK clock fall time, VIH(max) to VIL(min) GTX_CLK125 clock period GTX_CLK125 reference clock duty cycle measured at LVDD/2
Symbol1 tGTX tGTXH/tGTX tGTKHDX tGTKHDV tGTXR tGTXF tG125 tG125H/tG125
Min -- 40 0.5 -- -- -- -- 45
Typ 8.0 -- -- -- -- 8.0 --
Max -- 60 -- 5.0 1.0 1.0 -- 55
Unit ns % ns ns ns ns %
Notes
3
2 2
Notes: 1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming convention. 3. In rev 2.0 silicon, due to errata, tGTKHDX minimum and tGTKHDV maximum are not supported when the GTX_CLK is selected. Please refer to QE_ENET18 in the device errata document.
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Figure 9 shows the GMII transmit AC timing diagram.
tGTX GTX_CLK tGTXH TXD[7:0] TX_EN TX_ER tGTKHDX tGTXF tGTXR
Figure 9. GMII Transmit AC Timing Diagram
8.2.1.2
GMII Receive AC Timing Specifications
Table 28. GMII Receive AC Timing Specifications
Table 28 provides the GMII receive AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time, VIL(min) to VIH(max) RX_CLK clock fall time, VIH(max) to VIL(min)
Symbol 1 tGRX tGRXH/tGRX tGRDVKH tGRDXKH tGRXR tGRXF
Min -- 40 2.0 0.2 -- --
Typ 8.0 -- -- -- -- --
Max -- 60 -- -- 1.0 1.0
Unit ns % ns ns ns ns
Notes
2
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. In rev 2.0 silicon, due to errata, tGRDXKH minimum is 0.5 which is not compliant with the standard. Please refer to QE_ENET18 in the device errata document.
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Figure 10 shows the GMII receive AC timing diagram.
tGRX RX_CLK tGRXH RXD[7:0] RX_DV RX_ER tGRDXKH tGRDVKH tGRXF tGRXR
Figure 10. GMII Receive AC Timing Diagram
8.2.2
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.2.1
MII Transmit AC Timing Specifications
Table 29. MII Transmit AC Timing Specifications
Table 29 provides the MII transmit AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise time, VIL(min) to VIH(max) TX_CLK data clock fall time, VIH(max) to VIL(min)
Symbol1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTKHDV tMTXR tMTXF
Min -- -- 35 1 -- 1.0 1.0
Typ 400 40 -- 5 -- --
Max -- -- 65 -- 15 4.0 4.0
Unit ns ns % ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 11 shows the MII transmit AC timing diagram.
tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR
Figure 11. MII Transmit AC Timing Diagram
8.2.2.2
MII Receive AC Timing Specifications
Table 30. MII Receive AC Timing Specifications
Table 30 provides the MII receive AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time, VIL(min) to VIH(max) RX_CLK clock fall time, VIH(max) to VIL(min)
Symbol1 tMRX tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR tMRXF
Min -- -- 35 10.0 10.0 1.0 1.0
Typ 400 40 -- -- -- -- --
Max -- -- 65 -- -- 4.0 4.0
Unit ns ns % ns ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 12 provides the AC test load.
Output Z0 = 50 RL = 50 LVDD/2
Figure 12. AC Test Load
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Figure 13 shows the MII receive AC timing diagram.
tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKH tMRXF Valid Data tMRXR
Figure 13. MII Receive AC Timing Diagram
8.2.3
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.3.1
RMII Transmit AC Timing Specifications
Table 31. RMII Transmit AC Timing Specifications
Table 31 provides the RMII transmit AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition REF_CLK clock REF_CLK duty cycle REF_CLK to RMII data TXD[1:0], TX_EN delay REF_CLK data clock rise time, VIL(min) to VIH(max) REF_CLK data clock fall time, VIH(max) to VIL(min)
Symbol1 tRMX tRMXH/tRMX tRMTKHDX tRMTKHDV tRMXR tRMXF
Min -- 35 2 -- 1.0 1.0
Typ 20 -- -- -- --
Max -- 65 -- 10 4.0 4.0
Unit ns % ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 14 shows the RMII transmit AC timing diagram.
tRMX REF_CLK tRMXH TXD[1:0] TX_EN tRMTKHDX tRMXF tRMXR
Figure 14. RMII Transmit AC Timing Diagram
8.2.3.2
RMII Receive AC Timing Specifications
Table 32. RMII Receive AC Timing Specifications
Table 32 provides the RMII receive AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition REF_CLK clock period REF_CLK duty cycle RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK REF_CLK clock rise time, VIL(min) to VIH(max) REF_CLK clock fall time, VIH(max) to VIL(min)
Symbol1 tRMX tRMXH/tRMX tRMRDVKH tRMRDXKH tRMXR tRMXF
Min -- 35 4.0 2.0 1.0 1.0
Typ 20 -- -- -- -- --
Max -- 65 -- -- 4.0 4.0
Unit ns % ns ns ns ns
Note: 1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 15 provides the AC test load.
Output Z0 = 50 RL = 50 LVDD/2
Figure 15. AC Test Load
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UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 16 shows the RMII receive AC timing diagram.
tRMX REF_CLK tRMXH RXD[1:0] CRS_DV RX_ER tRMRDVKH tRMRDXKH tRMXF Valid Data tRMXR
Figure 16. RMII Receive AC Timing Diagram
8.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.2.4.1
TBI Transmit AC Timing Specifications
Table 33. TBI Transmit AC Timing Specifications
Table 33 provides the TBI transmit AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to TBI data TCG[9:0] delay GTX_CLK clock rise time, VIL(min) to VIH(max) GTX_CLK clock fall time, VIH(max) to VIL(min) GTX_CLK125 reference clock period GTX_CLK125 reference clock duty cycle
Symbol1 tTTX tTTXH/tTTX tTTKHDX tTTKHDV tTTXR tTTXF tG125 tG125H/tG125
Min -- 40 1.0 -- -- -- -- 45
Typ 8.0 -- -- -- -- 8.0 --
Max -- 60 -- 5.0 1.0 1.0 -- 55
Unit ns % ns ns ns ns ns
Notes
3
2
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention. 3. In rev 2.0 silicon, due to errata, tTTKHDX minimum is 0.7 ns for UCC1. Please refer to QE_ENET19 in the device errata document.
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Figure 17 shows the TBI transmit AC timing diagram.
tTTX GTX_CLK tTTXH TXD[7:0] TX_EN TX_ER tTTKHDX tTTXF tTTXR
Figure 17. TBI Transmit AC Timing Diagram
8.2.4.2
TBI Receive AC Timing Specifications
Table 34. TBI Receive AC Timing Specifications
Table 34 provides the TBI receive AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition PMA_RX_CLK clock period PMA_RX_CLK skew RX_CLK duty cycle RCG[9:0] setup time to rising PMA_RX_CLK RCG[9:0] hold time to rising PMA_RX_CLK RX_CLK clock rise time, VIL(min) to VIH(max) RX_CLK clock fall time, VIH(max) to VIL(min)
Symbol1 tTRX tSKTRX tTRXH/tTRX tTRDVKH tTRDXKH tTRXR tTRXF
Min
Typ 16.0
Max
Unit ns
Notes
7.5 40 2.5 1.0 0.7 0.7
-- -- -- -- -- --
8.5 60 -- -- 2.4 2.4
ns % ns ns ns ns 2 2
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Setup and hold time of even numbered RCG are measured from riding edge of PMA_RX_CLK1. Setup and hold time of odd numbered RCG are measured from riding edge of PMA_RX_CLK0.
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Figure 18 shows the TBI receive AC timing diagram.
tTRX PMA_RX_CLK1 tTRXH RCG[9:0] tTRDVKH tSKTRX PMA_RX_CLK0 tTRXH tTRDVKH tTRDXKH tTRDXKH tTRXF Even RCG Odd RCG tTRXR
Figure 18. TBI Receive AC Timing Diagram
8.2.5
RGMII and RTBI AC Timing Specifications
Table 35. RGMII and RTBI AC Timing Specifications
Table 35 presents the RGMII and RTBI AC timing specifications.
At recommended operating conditions with LVDD of 2.5 V 5%.
Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock cycle duration Duty cycle for 1000Base-T Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%-80%) Fall time (20%-80%) GTX_CLK125 reference clock period
Symbol1 tSKRGTKHDX tSKRGTKHDV tSKRGDXKH tSKRGDVKH tRGT tRGTH/tRGT tRGTH/tRGT tRGTR tRGTF tG125
Min -0.5 -- 1.0 -- 7.2 45 40 -- -- --
Typ -- -- 8.0 50 50 -- -- 8.0
Max -- 0.5 -- 2.6 8.8 55 60 0.75 0.75 --
Unit ns ns ns % % ns ns ns
Notes 7 2 3 4, 5 3, 5
6
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Table 35. RGMII and RTBI AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 2.5 V 5%.
GTX_CLK125 reference clock duty cycle
tG125H/tG125
47
--
53
%
Notes: 1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. 5. Duty cycle reference is LVDD/2. 6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention. 7. In rev 2.0 silicon, due to errata, tSKRGTKHDX minimum is -2.3 ns and tSKRGTKHDV maximum is 1 ns for UCC1, 1.2 ns for UCC2 option 1, and 1.8 for UCC2 option 2. In rev2.1 silicon, due to errata, tSKRGTKHDX minimum is -0.65 ns for UCC2 option 1 and -0.9 for UCC2 option 2, and tSKRGTKHDV maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2 option 2. Please refer to QE_ENET10 in the device errata document. UCC1 does meet tSKRGTKHDX minimum for rev2.1 silicon.
Figure 19 shows the RGMII and RTBI AC timing and multiplexing diagrams.
tRGT tRGTH GTX_CLK (At Transmitter) tSKRGTKHDX TXD[8:5][3:0] TXD[7:4][3:0] TXD[3:0] TXD[8:5] TXD[7:4] TXD[9] TXERR tSKRGTKHDX TX_CLK (At PHY)
TX_CTL
TXD[4] TXEN
RXD[8:5][3:0] RXD[7:4][3:0]
RXD[8:5] RXD[3:0] RXD[7:4] tSKRGTKHDX RXD[4] RXDV RXD[9] RXERR tSKRGTKHDX
RX_CTL
RX_CLK (At PHY)
Figure 19. RGMII and RTBI AC Timing and Multiplexing Diagrams
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8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for GMII, RGMII, TBI and RTBI are specified in Section 8.1, "Three-Speed Ethernet Controller (10/100/1000 Mbps)-- GMII/MII/RMII/TBI/RGMII/RTBI Electrical Characteristics."
8.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 36.
Table 36. MII Management DC Electrical Characteristics when powered at 3.3V
Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol OVDD VOH VOL VIH VIL IIN IOH = -1.0 mA IOL = 1.0 mA -- -- 0 V VIN OVDD Conditions -- OVDD = Min OVDD = Min Min 2.97 2.10 GND 2.00 -- -- Max 3.63 OVDD + 0.3 0.50 -- 0.80 10 Unit V V V V V A
8.3.2
MII Management AC Electrical Specifications
Table 37. MII Management AC Timing Specifications
Table 37 provides the MII management AC timing specifications.
At recommended operating conditions with LVDD is 3.3 V 10%
Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time
Symbol1 fMDC tMDC tMDCH tMDTKHDX tMDTKHDV tMDRDVKH tMDRDXKH tMDCR
Min -- -- 32 10 -- 10 0 --
Typ 2.5 400 -- -- -- -- --
Max -- -- -- -- 110 -- -- 10
Unit MHz ns ns ns ns ns ns
Notes 2
3
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Table 37. MII Management AC Timing Specifications (continued)
At recommended operating conditions with LVDD is 3.3 V 10%
Parameter/Condition MDC fall time
Symbol1 tMDHF
Min --
Typ --
Max 10
Unit ns
Notes
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDRDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz). 3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay is 90 ns and for a ce_clk of 300 MHz, the delay is 63 ns).
Figure 20 shows the MII management AC timing diagram.
tMDC MDC tMDCH MDIO (Input) tMDRDVKH tMDRDXKH MDIO (Output) tMDTKHDX tMDHF tMDCR
Figure 20. MII Management Interface Timing Diagram
8.3.3
IEEE Std. 1588TM Timer AC Specifications
Table 38. 1588 Timer AC Specifications
Parameter Symbol tTMRCK tTMRCKS tTMRCKH tGCLKNV Min 0 -- -- 0 Max 70 -- -- 6 Unit MHz -- -- ns Notes 1 2,3 2,3
Table 38 provides the IEEE Std. 1588 timer AC specifications.
Timer clock cycle time Input Setup to timer clock Input Hold from timer clock Output clock to output valid
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Local Bus
Table 38. 1588 Timer AC Specifications (continued)
Parameter Timer alarm to output valid Symbol tTMRAL Min -- Max -- Unit -- Notes 2
Notes: 1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected. Min and Max requirement for both rtc_clock and tmr_clock are the same. 2. These are asynchronous signals. 3. Inputs need to be stable at least one TMR clock.
9
Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the MPC8360E/58E.
9.1
Local Bus DC Electrical Characteristics
Table 39. Local Bus DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A Input current Symbol VIH VIL VOH VOL IIN Min 2 -0.3 OV DD - 0.4 -- -- Max OVDD + 0.3 0.8 -- 0.2 10 Unit V V V V A
Table 39 provides the DC electrical characteristics for the local bus interface.
9.2
Local Bus AC Electrical Specifications
Table 40. Local Bus General Timing Parameters--DLL Enabled
Parameter Symbol1 tLBK tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT1 tLBOTOT2 Min 7.5 1.7 1.9 1.0 1.0 1.5 3.0 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns Notes 2 3, 4 3, 4 3, 4 3, 4 5 6
Table 40 describes the general timing parameters of the local bus interface of the device.
Local bus cycle time Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time)
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Local Bus
Table 40. Local Bus General Timing Parameters--DLL Enabled (continued)
Parameter LALE output fall to LAD output transition (LATCH hold time) Local bus clock to LALE rise Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high impedance for LAD/LDP Symbol1 tLBOTOT3 tLBKHLR tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOX1 tLBKHOX2 tLBKHOZ Min 2.5 -- -- -- -- 1.0 1.0 -- Max -- 4.5 4.5 4.5 4.5 -- -- 3.8 Unit ns ns ns ns ns ns ns ns 3 3 3 3 Notes 7
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to rising edge of LSYNC_IN. 3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 x OVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5.tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10pF less than the load on LAD output pins. 6.tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10pF less than the load on LAD output pins. 7.tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output pins. 8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.
Table 41 describes the general timing parameters of the local bus interface of the device.
Table 41. Local Bus General Timing Parameters--DLL Bypass Mode
Parameter Local bus cycle time Input setup to local bus clock Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to output valid Symbol1 tLBK tLBIVKH tLBIXKH tLBOTOT1 tLBOTOT2 tLBOTOT3 tLBKHOV Min 15 7 1.0 1.5 3 2.5 -- Max -- -- -- -- -- -- 3 Unit ns ns ns ns ns ns ns Notes 2 3, 4 3, 4 5 6 7 3
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 41
Local Bus
Table 41. Local Bus General Timing Parameters--DLL Bypass Mode (continued)
Parameter Local bus clock to output high impedance for LAD/LDP Symbol1 tLBKHOZ Min -- Max 4 Unit ns Notes
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of LCLK0 (for all other inputs). 3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 x OVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5.tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10pF less than the load on LAD output pins. 6.tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10pF less than the load on LAD output pins. 7.tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output pins. 8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 9. DLL bypass mode is not recommended for use at frequencies above 66MHz.
Figure 21 provides the AC test load for the local bus.
Output Z0 = 50 RL = 50 OVDD/2
Figure 21. Local Bus C Test Load
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Local Bus
Figure 22 through Figure 27 show the local bus signals.
LSYNC_IN tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV Output (Address) Signal: LAD[0:31] tLBKHLR LALE tLBOTOT tLBKHOZ tLBKHOX tLBKHOV tLBKHOX tLBIXKH
tLBKHOV
tLBKHOZ tLBKHOX
Figure 22. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
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Local Bus
LCLK[n] tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] tLBIVKH Input Signal: LGTA tLBIXKH Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ Output Signals: LAD[0:31]/LDP[0:3] tLBOTOT LALE tLBKHOV tLBIXKH tLBIXKH
tLBKHOV
tLBKHOZ
Figure 23. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
LSYNC_IN
T1 T3 tLBKHOV1 GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1 tLBIXKH2 tLBKHOZ1
Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 44 Freescale Semiconductor
Local Bus
LCLK
T1 T3 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ
Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5]
tLBKHOZ
Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 45
Local Bus
LCLK
T1 T2 T3 T4 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ
Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5]
tLBKHOZ
Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode)
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 46 Freescale Semiconductor
JTAG
LSYNC_IN
T1 T2 T3 T4 tLBKHOV1 GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1 tLBIXKH2 tLBKHOZ1
Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled)
10 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MPC8360E/58E.
10.1
JTAG DC Electrical Characteristics
Table 42. JTAG interface DC Electrical Characteristics
Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = -6.0 mA IOL = 6.0 mA IOL = 3.2 mA -- -- 0 V VIN OVDD Min 2.4 -- -- 2.5 -0.3 -- Max -- 0.5 0.4 OVDD + 0.3 0.8 10 Unit V V V V V A
Table 42 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the device.
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 47
JTAG
This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the device. Table 43 provides the JTAG AC timing specifications as defined in Figure 29 through Figure 32.
Table 43. JTAG AC Timing Specifications (Independent of CLKIN)1
At recommended operating conditions (see Table 2).
Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock duty cycle JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO Output hold times: Boundary-scan data TDO JTAG external clock to output high impedance: Boundary-scan data TDO
Symbol 2 fJTG tJTG tJTKHKL/tJTG tJTGR & tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV tJTKLDX tJTKLOX tJTKLDZ tJTKLOZ
Min 0 30 45 0 25 4 4 10 10 2 2 2 2 2 2
Max 33.3 -- 55 2 -- -- --
Unit MHz ns % ns ns ns
Notes
3 4
ns -- -- ns 11 11 ns -- -- ns 19 9 5, 6 6 5 5 4
Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 21). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design and characterization.
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JTAG
Figure 28 provides the AC test load for TDO and the boundary-scan outputs of the device.
Output Z0 = 50 RL = 50 OVDD/2
Figure 28. AC Test Load for the JTAG Interface
Figure 29 provides the JTAG clock input timing diagram.
JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (OVDD/2) VM VM tJTGR tJTGF
Figure 29. JTAG Clock Input Timing Diagram
Figure 30 provides the TRST timing diagram.
TRST VM tTRST VM = Midpoint Voltage (OVDD /2) VM
Figure 30. TRST Timing Diagram
Figure 31 provides the boundary-scan timing diagram.
JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OV DD/2) Output Data Valid Input Data Valid VM
Figure 31. Boundary-Scan Timing Diagram
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I2C
Figure 32 provides the test access port timing diagram.
JTAG External Clock VM tJTIVKH tJTIXKH TDI, TMS tJTKLOV tJTKLOX TDO tJTKLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM
Figure 32. Test Access Port Timing Diagram
11 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8360E/58E.
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I2C
11.1
I2C DC Electrical Characteristics
Table 44. I2C DC Electrical Characteristics
Table 44 provides the DC electrical characteristics for the I2C interface of the device.
At recommended operating conditions with OVDD of 3.3 V 10%.
Parameter Input high voltage level Input low voltage level Low level output voltage Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10 to 400 pF Pulse width of spikes which must be suppressed by the input filter Capacitance for each I/O pin Input current (0 V VIN OV DD)
Symbol VIH VIL VOL tI2KLKV tI2KHKL CI IIN
Min 0.7 x OV DD -0.3 0 20 + 0.1 x CB 0 -- --
Max OVDD + 0.3 0.3 x OV DD 0.4 250 50 10 10
Unit V V V ns ns pF A
Notes
1 2 3
4
Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. CB = capacitance of one bus line in pF. 3. Refer to the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for information on the digital filter used. 4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
11.2
I2C AC Electrical Specifications
Table 45. I2C AC Electrical Specifications
Table 45 provides the AC timing parameters for the I2C interface of the device.
All values refer to VIH (min) and VIL (max) levels (see Table 44).
Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: CBUS compatible masters I2C bus devices Rise time of both SDA and SCL signals
Symbol1 fI2C tI2CL tI2CH tI2SVKH tI2SXKL tI2DVKH tI2DXKL
Min 0 1.3 0.6 0.6 0.6 100 -- 02
Max 400 -- -- -- -- -- -- 0.9 3 300
Unit kHz s s s s s
tI2CR
20 + 0.1 Cb 4
ns
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I2C
Table 45. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 44).
Parameter Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis)
Symbol1 tI2CF tI2PVKH tI2KHDX VNL VNH
Min 20 + 0.1 Cb 4 0.6 1.3 0.1 x OV DD 0.2 x OV DD
Max 300 -- -- -- --
Unit ns s s V V
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF.
Figure 33 provides the AC test load for the I2C.
Output Z0 = 50 RL = 50 OVDD/2
Figure 33. I2C AC Test Load
Figure 34 shows the AC timing diagram for the I2C bus.
SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL tI2CH Sr tI2SVKH tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF
Figure 34. I2C Bus AC Timing Diagram
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PCI
12 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8360E/58E.
12.1
PCI DC Electrical Characteristics
Table 46. PCI DC Electrical Characteristics
Parameter Symbol VIH VIL VOH VOL IIN Test Condition VOUT VOH (min) or VOUT VOL (max) IOH = -500 A IOL = 1500 A 0V VIN1 OVDD Min 0.5 x OVDD -0.5 0.9 x OVDD -- -- Max OVDD + 0.5 0.3 x OVDD -- 0.1 x OVDD 10 Unit V V V V A
Table 46 provides the DC electrical characteristics for the PCI interface of the device.
High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current
Notes: 1. Note that the symbol VIN, in this case, represents the OV IN symbol referenced in Table 1 and Table 2.
12.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the device. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the device is configured as a host or agent device. Table 47 provides the PCI AC timing specifications at 66 MHz.
.
Table 47. PCI AC Timing Specifications at 66 MHz
Parameter Clock to output valid Output hold from Clock Clock to output high impedance Input setup to Clock Symbol 1 tPCKHOV tPCKHOX tPCKHOZ tPCIVKH Min -- 1 -- 3.0 Max 6.0 -- 14 -- Unit ns ns ns ns Notes 2, 5 2 2, 3 2, 4
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PCI
Table 47. PCI AC Timing Specifications at 66 MHz (continued)
Parameter Input hold from Clock Symbol 1 tPCIXKH Min 0.3 Max -- Unit ns Notes 2, 4, 6
Notes: 1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications. 3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. 5. In rev 2.0 silicon, due to errata, tPCIHOV maximum is 6.6ns. Please refer to PCI21 in the device errata document. 6. In rev 2.0 silicon, due to errata, tPCIXKH minimum is 1 ns. Please refer to PCI17 in the device errata document.
Table 48. PCI AC Timing Specifications at 33 MHz
Parameter Clock to output valid Output hold from Clock Clock to output high impedance Input setup to Clock Input hold from Clock Symbol 1 tPCKHOV tPCKHOX tPCKHOZ tPCIVKH tPCIXKH Min -- 2 -- 7.0 0.3 Max 11 -- 14 -- -- Unit ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4, 5
Notes: 1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications. 3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. 5. In rev 2.0 silicon, due to errata, tPCIXKH minimum is 1 ns. Please refer to PCI17 in the device errata document.
Figure 35 provides the AC test load for PCI.
Output Z0 = 50 RL = 50 OVDD/2
Figure 35. PCI AC Test Load
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Timers
Figure 36 shows the PCI input AC timing conditions.
CLK tPCIVKH tPCIXKH Input
Figure 36. PCI Input AC Timing Measurement Conditions
Figure 37 shows the PCI output AC timing conditions.
CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output
tPCKHOX
Figure 37. PCI Output AC Timing Measurement Condition
13 Timers
This section describes the DC and AC electrical specifications for the timers of the MPC8360E/58E.
13.1
Timers DC Electrical Characteristics
Table 49 provides the DC electrical characteristics for the device timer pins, including TIN, TOUT, TGATE and RTC_CLK.
Table 49. Timers DC Electrical Characteristics
Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = -6.0 mA IOL = 6.0 mA IOL = 3.2 mA -- -- 0 V VIN OVDD Min 2.4 -- -- 2.0 -0.3 -- Max -- 0.5 0.4 OVDD + 0.3 0.8 10 Unit V V V V V A
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 55
GPIO
13.2
Timers AC Timing Specifications
Table 50. Timers Input AC Timing Specifications1
Characteristic Symbol 2 tTIWID Typ 20 Unit ns
Table 50 provides the timer input and output AC timing specifications.
Timers inputs--minimum pulse width
Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers inputs are required to be valid for at least tTIWID ns to ensure proper operation.
Figure 38 provides the AC test load for the timers.
Output Z0 = 50 RL = 50 OVDD/2
Figure 38. Timers AC Test Load
14 GPIO
This section describes the DC and AC electrical specifications for the GPIO of the MPC8360E/58E.
14.1
GPIO DC Electrical Characteristics
Table 51. GPIO DC Electrical Characteristics
Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = -6.0 mA IOL = 6.0 mA IOL = 3.2 mA -- -- 0 V VIN OVDD Min 2.4 -- -- 2.0 -0.3 -- Max -- 0.5 0.4 OVDD + 0.3 0.8 10 Unit V V V V V A Notes 1 1 1 1
Table 51 provides the DC electrical characteristics for the device GPIO.
Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current
Note: This specification applies when operating from 3.3V supply.
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IPIC
14.2
GPIO AC Timing Specifications
Table 52. GPIO Input AC Timing Specifications1
Characteristic Symbol 2 tPIWID Typ 20 Unit ns
Table 52 provides the GPIO input and output AC timing specifications.
GPIO inputs--minimum pulse width
Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
Figure 39 provides the AC test load for the GPIO.
Output Z0 = 50 RL = 50 OVDD/2
Figure 39. GPIO AC Test Load
15 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8360E/58E.
15.1
IPIC DC Electrical Characteristics
Table 53. IPIC DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Output low voltage Output low voltage Symbol VIH VIL IIN VOL VOL IOL = 6.0 mA IOL = 3.2 mA -- -- Condition Min 2.0 -0.3 Max OVDD + 0.3 0.8 10 0.5 0.4 Unit V V A V V
Table 53 provides the DC electrical characteristics for the external interrupt pins of the IPIC.
Notes: 1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT, and CE ports Interrupts. 2. IRQ_OUT and MCP_OUT are open drain pins, thus VOH is not relevant for those pins.
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SPI
15.2
IPIC AC Timing Specifications
Table 54. IPIC Input AC Timing Specifications1
Characteristic Symbol 2 tPIWID Min 20 Unit ns
Table 54 provides the IPIC input and output AC timing specifications.
IPIC inputs--minimum pulse width
Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2.IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge triggered mode.
16 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8360E/58E.
16.1
SPI DC Electrical Characteristics
Table 55. SPI DC Electrical Characteristics
Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = -6.0 mA IOL = 6.0 mA IOL = 3.2 mA -- -- 0 V VIN OVDD Min 2.4 -- -- 2.0 -0.3 -- Max -- 0.5 0.4 OVDD + 0.3 0.8 10 Unit V V V V V A
Table 55 provides the DC electrical characteristics for the device SPI.
16.2
SPI AC Timing Specifications
Table 56. SPI AC Timing Specifications1
Characteristic Symbol 2 tNIKHOX tNIKHOV tNEKHOX tNEKHOV tNIIVKH tNIIXKH Min 0.3 -- 2 -- 8 0 Max -- 8 -- 8 -- -- Unit ns ns ns ns
Table 56 and provide the SPI input and output AC timing specifications.
SPI outputs--Master mode (internal clock) delay SPI outputs--Slave mode (external clock) delay SPI inputs--Master mode (internal clock) input setup time SPI inputs--Master mode (internal clock) input hold time
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SPI
Table 56. SPI AC Timing Specifications1
Characteristic SPI inputs--Slave mode (external clock) input setup time SPI inputs--Slave mode (external clock) input hold time Symbol 2 tNEIVKH tNEIXKH Min 4 2 Max -- -- Unit ns ns
Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V).
Figure 40 provides the AC test load for the SPI.
Output Z0 = 50 RL = 50 OVDD/2
Figure 40. SPI AC Test Load
Figure 41 through Figure 42 represent the AC timing from Table 56. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 41 shows the SPI timing in slave mode (external clock).
SPICLK (input) tNEIVKH tNEIXKH
Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note)
tNEKHOV
Note: The clock edge is selectable on SPI.
Figure 41. SPI AC Timing in Slave mode (External Clock) Diagram
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TDM/SI
Figure 42 shows the SPI timing in Master mode (internal clock).
SPICLK (output) tNIIVKH tNIIXKH
Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note)
tNIKHOV
Note: The clock edge is selectable on SPI.
Figure 42. SPI AC Timing in Master mode (Internal Clock) Diagram
17 TDM/SI
This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial interface of the MPC8360E/58E.
17.1
TDM/SI DC Electrical Characteristics
Table 57. TDM/SI DC Electrical Characteristics
Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VIH VIL IIN Condition IOH = -2.0 mA IOL = 3.2 mA -- -- 0 V VIN OV DD Min 2.4 -- 2.0 -0.3 -- Max -- 0.5 OVDD + 0.3 0.8 10 Unit V V V V A
Table 57 provides the DC electrical characteristics for the device TDM/SI.
17.2
TDM/SI AC Timing Specifications
Table 58. TDM/SI AC Timing Specifications1
Characteristic Symbol2 tSEKHOV tSEKHOX tSEIVKH Min 2 2 5 Max3 10 10 -- Unit ns ns ns
Table 58 provides the TDM/SI input and output AC timing specifications.
TDM/SI outputs--External clock delay TDM/SI outputs--External clock high impedance TDM/SI inputs--External clock input setup time
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TDM/SI
Table 58. TDM/SI AC Timing Specifications1 (continued)
Characteristic TDM/SI inputs--External clock input hold time Symbol2 tSEIXKH Min 2 Max3 -- Unit ns
Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). 3. Timings are measured from the positive or negative edge of the clock, according to SIxMR [CE] and SITXCEI[TXCEIx]. See the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more details.
Figure 43 provides the AC test load for the TDM/SI.
Output Z0 = 50 RL = 50 OVDD/2
Figure 43. TDM/SI AC Test Load
Figure 44 represents the AC timing from Table 56. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 44 shows the TDM/SI timing with external clock.
TDM/SICLK (input) tSEIVKH tSEIXKH
Input Signals: TDM/SI (See Note) Output Signals: TDM/SI (See Note)
tSEKHOV
tSEKHOX
Note: The clock edge is selectable on TDM/SI
Figure 44. TDM/SI AC Timing (External Clock) Diagram
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UTOPIA/POS
18 UTOPIA/POS
This section describes the DC and AC electrical specifications for the UTOPIA/POS of the MPC8360E/58E.
18.1
UTOPIA/POS DC Electrical Characteristics
Table 59. UTOPIA DC Electrical Characteristics
Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VIH VIL IIN Condition IOH = -8.0 mA IOL = 8.0 mA -- -- 0 V VIN OVDD Min 2.4 -- 2.0 -0.3 -- Max -- 0.5 OVDD + 0.3 0.8 10 Unit V V V V A
Table 59 provides the DC electrical characteristics for the device UTOPIA.
18.2
Utopia/POS AC Timing Specifications
Table 60. UTOPIA AC Timing Specifications1
Characteristic Symbol 2 tUIKHOV tUEKHOV tUIKHOX tUEKHOX tUIIVKH tUEIVKH tUIIXKH tUEIXKH Min 0 1 0 1 6 4 2.4 1 Max 11.5 11.6 8.0 10.0 -- -- -- -- Unit ns ns ns ns ns ns ns ns 3 3 Notes
Table 60 provides the UTOPIA input and output AC timing specifications.
UTOPIA outputs--Internal clock delay UTOPIA outputs--External clock delay UTOPIA outputs--Internal clock High Impedance UTOPIA outputs--External clock High Impedance UTOPIA inputs--Internal clock input setup time UTOPIA inputs--External clock input setup time UTOPIA inputs--Internal clock input Hold time UTOPIA inputs--External clock input hold time
Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUIKHOX symbolizes the UTOPIA outputs internal timing (UI) for the time tUTOPIA memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). 3. In rev 2.0 silicon, due to errata, tUEIVKH minimum is 4.3 ns and tUEIXKH minimum is 1.4 ns under specific conditions. Please refer to QE_UPC3 in the device errata document.
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HDLC, BISYNC, Transparent, and Synchronous UART
Figure 45 provides the AC test load for the UTOPIA.
Output Z0 = 50 RL = 50 OVDD/2
Figure 45. UTOPIA AC Test Load
Figure 46 and Figure 47 represent the AC timing from Table 56. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 46 shows the UTOPIA timing with external clock.
UtopiaCLK (input) tUEIVKH tUEIXKH
Input Signals: UTOPIA
Output Signals: UTOPIA
tUEKHOV
tUEKHOX
Figure 46. UTOPIA AC Timing (External Clock) Diagram
Figure 47 shows the UTOPIA timing with internal clock.
UtopiaCLK (output) tUIIVKH tUIIXKH
Input Signals: UTOPIA
Output Signals: UTOPIA
tUIKHOV
tUIKHOX
Figure 47. UTOPIA AC Timing (Internal Clock) Diagram
19 HDLC, BISYNC, Transparent, and Synchronous UART
This section describes the DC and AC electrical specifications for the high level data link control (HDLC), BiSync, transparent, and synchronous UART protocols of the MPC8360E/58E.
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HDLC, BISYNC, Transparent, and Synchronous UART
19.1
HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics
Table 61 provides the DC electrical characteristics for the device HDLC, BISYNC, transparent, and synchronous UART protocols.
Table 61. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics
Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VIH VIL IIN Condition IOH = -2.0 mA IOL = 3.2 mA -- -- 0 V VIN OVDD Min 2.4 -- 2.0 -0.3 -- Max -- 0.5 OVDD + 0.3 0.8 10 Unit V V V V A
19.2
HDLC, BISYNC, Transparent, and Synchronous UART AC Timing Specifications
Table 62 and Table 63 provide the input and output AC timing specifications for HDLC, BiSync, transparent, and synchronous UART protocols.
Table 62. HDLC, BISYNC, and Transparent AC Timing Specifications1
Characteristic Outputs--Internal clock delay Outputs--External clock delay Outputs--Internal clock High Impedance Outputs--External clock High Impedance Inputs--Internal clock input setup time Inputs--External clock input setup time Inputs--Internal clock input Hold time Inputs--External clock input hold time Symbol2 tHIKHOV tHEKHOV tHIKHOX tHEKHOX tHIIVKH tHEIVKH tHIIXKH tHEIXKH Min 0 1 -0.5 1 8.5 4 1.4 1 Max 11.2 10.8 5.5 8 -- -- -- -- Unit ns ns ns ns ns ns ns ns
Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
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HDLC, BISYNC, Transparent, and Synchronous UART
Table 63. Synchronous UART AC Timing Specifications1
Characteristic Outputs--Internal clock delay Outputs--External clock delay Outputs--Internal clock High Impedance Outputs--External clock High Impedance Inputs--Internal clock input setup time Inputs--External clock input setup time Inputs--Internal clock input Hold time Inputs--External clock input hold time Symbol2 tUAIKHOV tUAEKHOV tUAIKHOX tUAEKHOX tUAIIVKH tUAEIVKH tUAIIXKH tUAEIXKH Min 0 1 0 1 6 8 1 1 Max 11.3 14 11 14 -- -- -- -- Unit ns ns ns ns ns ns ns ns
Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
Figure 48 provides the AC test load.
Output Z0 = 50 RL = 50 OVDD/2
Figure 48. AC Test Load
19.3
AC Test Load
Figure 49 and Figure 50 represent the AC timing from Table 62 and Table 63. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
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HDLC, BISYNC, Transparent, and Synchronous UART
Figure 49 shows the timing with external clock.
Serial CLK (input) tHEIVKH tHEIXKH
Input Signals: (See Note) Output Signals: (See Note)
tHEKHOV
tHEKHOX
Note: The clock edge is selectable.
Figure 49. AC Timing (External Clock) Diagram
Figure 50 shows the timing with internal clock.
Serial CLK (output) tHIIVKH tHIIXKH
Input Signals: (See Note) Output Signals: (See Note)
tHIKHOV
tHIKHOX Note: The clock edge is selectable.
Figure 50. AC Timing (Internal Clock) Diagram
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 66 Freescale Semiconductor
USB
20 USB
This section provides the AC and DC electrical specifications for the USB interface of the MPC8360E/58E.
20.1
USB DC Electrical Characteristics
Table 64. USB DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A Input current Symbol VIH VIL VOH VOL IIN Min 2 -0.3 OVDD - 0.4 -- -- Max OVDD + 0.3 0.8 -- 0.2 10 Unit V V V V A
Table 64 provides the DC electrical characteristics for the USB interface.
Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
20.2
USB AC Electrical Specifications
Table 65. USB General Timing Parameters
Parameter usb clock cycle time usb clock cycle time skew between TXP and TXN skew among RXP, RXN and RXD skew among RXP, RXN and RXD Symbol 1 tUSCK tUSCK tUSTSPN tUSRSPND tUSRPND Min 20.83 166.67 -- -- -- Max -- -- 5 10 100 Unit ns ns ns ns ns full speed transitions low speed transitions Notes full speed 48MHz low speed 6MHz
Table 65 describes the general timing parameters of the USB interface of the device.
Notes: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(state) (signal) for receive signals and t(First two letters of functional block)(state)(signal) for transmit signals. For example, tUSRSPND symbolizes usb timing (US) for the usb receive signals skew (RS) among RXP, RXN, and RXD (PND). Also, tUSTSPN symbolizes usb timing (US) for the usb transmit signals skew (TS) between TXP and TXN (PN). 2.Skew measurements are done at OVDD/2 of the rising or falling edge of the signals.
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 67
Package and Pin Listings
Figure 51 provide the AC test load for the USB.
Output Z0 = 50 RL = 50 OVDD/2
Figure 51. USB AC Test Load
21 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8360E/58E is available in a tape ball grid array (TBGA), see Section 21.1, "Package Parameters for the TBGA Package and Section 21.2, "Mechanical Dimensions of the TBGA Package," for information on the package.
21.1
Package Parameters for the TBGA Package
The package parameters for rev 2.0 silicon are as provided in the following list. The package type is 37.5 mm x 37.5 mm, 740 tape ball grid array (TBGA). Package outline 37.5 mm x 37.5 mm Interconnects 740 Pitch 1.00 mm Module height (typical) 1.46 mm Solder Balls 62 Sn/36 Pb/2 Ag (ZU package) 95.5 Sn/0.5 Cu/4Ag (VV package) Ball diameter (typical) 0.64 mm
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 68 Freescale Semiconductor
Package and Pin Listings
21.2
Mechanical Dimensions of the TBGA Package
Figure 52 depicts the mechanical dimensions and bottom surface nomenclature of the device, 740-TBGA package.
Figure 52. Mechanical Dimensions and Bottom Surface Nomenclature of the TBGA Package
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Package and Pin Listings
21.3
Pinout Listings
Table 66. MPC8360E TBGA Pinout Listing
Signal Package Pin Number Primary DDR SDRAM Memory Controller Interface Pin Type Power Supply Notes
Table 66 shows the pin list of the MPC8360E TBGA package.
MEMC1_MDQ[0:31]
AJ34, AK33, AL33, AL35, AJ33, AK34, AK32, AM36, AN37, AN35, AR34, AT34, AP37, AP36, AR36, AT35, AP34, AR32, AP32, AM31, AN33, AM34, AM33, AM30, AP31, AM27, AR30, AT32, AN29, AP29, AN27, AR29 AN8, AN7, AM8, AM6, AP9, AN9, AT7, AP7, AU6, AP6, AR4, AR3, AT6, AT5, AR5, AT3, AP4, AM5, AP3, AN3, AN5, AL5, AN4, AM2, AL2, AH5, AK3, AJ2, AJ3, AH4, AK4, AH3 AP24, AN22, AM19, AN19, AM24 AM23 AM22, AN18 AL36, AN34, AP33, AN28 AT9, AU4, AM3, AJ6 AP27 AK35, AP35, AN31, AM26 AT8, AU3, AL4, AJ5 AP26 AU29, AU30 AT30 AU21, AP22, AP21, AT21, AU25, AU26, AT23, AR26, AU24, AR23, AR28, AU23, AR22, AU20, AR18 AG33, AJ36 AT1, AK2 AT26 AT29 AT24 AU27, AT27 AU8, AU7 AL32, AU33 AK37, AT37 AN1, AR2
I/O
GVDD
MEMC1_MDQ[32:63]/ MEMC2_MDQ[0:31]
I/O
GVDD
MEMC1_MECC[0:4]/ MSRCID[0:4] MEMC1_MECC[5]/ MDVAL MEMC1_MECC[6:7] MEMC1_MDM[0:3] MEMC1_MDM[4:7]/ MEMC2_MDM[0:3] MEMC1_MDM[8] MEMC1_MDQS[0:3] MEMC1_MDQS[4:7]/ MEMC2_MDQS[0:3] MEMC1_MDQS[8] MEMC1_MBA[0:1] MEMC1_MBA[2] MEMC1_MA[0:14] MEMC1_MODT[0:1] MEMC1_MODT[2:3]/ MEMC2_MODT[0:1] MEMC1_MWE MEMC1_MRAS MEMC1_MCAS MEMC1_MCS[0:1] MEMC1_MCS[2:3]/ MEMC2_MCS[0:1] MEMC1_MCKE[0:1] MEMC1_MCK[0:1] MEMC1_MCK[2:3]/ MEMC2_MCK[0:1]
I/O I/O I/O O O O I/O I/O I/O O O O O O O O O O O O O O
GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD 3 6 6
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Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal MEMC1_MCK[4:5]/ MEMC2_MCKE[0:1] MEMC1_MCK[0:1] MEMC1_MCK[2:3]/ MEMC2_MCK[0:1] MEMC1_MCK[4]/ MEMC2_MDM[8] MEMC1_MCK[5]/ MEMC2_MDQS[8] MDIC[0:1] AN25, AK1 AL37, AT36 AP2, AT2 AN24 AL1 AH6, AP30 Secondary DDR SDRAM Memory Controller Interface MEMC2_MECC[0:7] MEMC2_MBA[0:2] MEMC2_MA[0:14] MEMC2_MWE MEMC2_MRAS MEMC2_MCAS AN16, AP18, AM16, AM17, AN17, AP13, AP15, AN13 AU12, AU15, AU13 AT12, AP11, AT13, AT14, AR13, AR15, AR16, AT16, AT18, AT17, AP10, AR20, AR17, AR14, AR11 AU10 AT11 AU11 PCI PCI_INTA/ IRQ_OUT/ CE_PF[5] PCI_RESET_OUT/ CE_PF[6] PCI_AD[31:30]/ CE_PG[31:30] PCI_AD[29:25]/ CE_PG[29:25] PCI_AD[24]/ CE_PG[24] PCI_AD[23:0]/ CE_PG[23:0] PCI_C/ BE[3:0]/ CE_PF[10:7] PCI_PAR/ CE_PF[11] PCI_FRAME/ CE_PF[12] PCI_TRDY/ CE_PF[13] A20 I/O LVDD2 2 I/O O O O O O GVDD GVDD GVDD GVDD GVDD GVDD Package Pin Number Pin Type O O O O O I/O Power Supply GVDD GVDD GVDD GVDD GVDD GVDD 10 Notes
E19 D20, D21 A24, B23, C23, E23, A26 B21 C24, C25, D25, B25, E24, F24, A27, A28, F27, A30, C30, D30, E29, B31, C31, D31, D32, A32, C33, B33, F30, E31, A34, D33 E22, B26, E28, F28
I/O I/O I/O I/O I/O
LVDD2 LVDD2 OVDD LVDD2 OVDD
I/O
OVDD
D28 D26 C27
I/O I/O I/O
OVDD OVDD OVDD 5 5
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Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal PCI_IRDY/ CE_PF[14] PCI_STOP/ CE_PF[15] PCI_DEVSEL/ CE_PF[16] PCI_IDSEL/ CE_PF[17] PCI_SERR/ CE_PF[18] PCI_PERR/ CE_PF[19] PCI_REQ[0]/ CE_PF[20] PCI_REQ[1]/ CPCI_HS_ES/ CE_PF[21] PCI_REQ[2]/ CE_PF[22] PCI_GNT[0]/ CE_PF[23] PCI_GNT[1]/ CPCI1_HS_LED/ CE_PF[24] PCI_GNT[2]/ CPCI1_HS_ENUM/ CE_PF[25] PCI_MODE M66EN/ CE_PF[4] C28 B28 E26 F22 B29 A29 F19 A21 Package Pin Number Pin Type I/O I/O I/O I/O I/O I/O I/O I/O Power Supply OVDD OVDD OVDD OVDD OVDD OVDD LVDD2 LVDD2 5 5 Notes 5 5 5
C21 E20 B20
I/O I/O I/O
LVDD2 LVDD2 LVDD2
C20
I/O
LVDD2
D36 B37 Local Bus Controller Interface
I I/O
OVDD OVDD
LAD[0:31]
N32, N33, N35, N36, P37, P32, P34, R36, R35, R34, R33, T37, T35, T34, T33, U37, T32, U36, U34, V36, V35, W37, W35, V33, V32, W34, Y36, W32, AA37, Y33, AA35, AA34 AB37 AB36 AB35 AA33 AC37, AA32, AC36, AC34, AD36 AD33, AG37, AF34, AE33, AD32, AH37
I/O
OVDD
LDP[0]/ CKSTOP_OUT LDP[1]/ CKSTOP_IN LDP[2]/ LCS[6] LDP[3]/ LCS[7] LA[27:31] LCS[0:5]
I/O I/O I/O I/O O O
OVDD OVDD OVDD OVDD OVDD OVDD
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Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal LWE[0:3]/ LSDDQM[0:3]/ LBS[0:3] LBCTL LALE LGPL0/ LSDA10/ cfg_reset_source0 LGPL1/ LSDWE/ cfg_reset_source1 LGPL2/ LSDRAS/ LOE LGPL3/ LSDCAS/ cfg_reset_source2 LGPL4/ LGTA/ LUPWAIT/ LPBSE LGPL5/ cfg_clkin_div LCKE LCLK[0] LCLK[1]/ LCS[6] LCLK[2]/ LCS[7] LSYNC_OUT LSYNC_IN Package Pin Number AG35, AG34, AH36, AE32 Pin Type O Power Supply OVDD Notes
AD35 M37 AB32
O O I/O
OVDD OVDD OVDD
AE37
I/O
OVDD
AC33
O
OVDD
AD34
I/O
OVDD
AE35
I/O
OVDD
AF36 G36 J33 J34 G37 F34 G35 Programmable Interrupt Controller
I/O O O O O O I
OVDD OVDD OVDD OVDD OVDD OVDD OVDD
MCP_OUT IRQ0/ MCP_IN IRQ[1]/ M1SRCID[4]/ M2SRCID[4]/ LSRCID[4] IRQ[2]/ M1DVAL/ M2DVAL/ LDVAL IRQ[3]/ CORE_SRESET
E34 C37 F35
O I I/O
OVDD OVDD OVDD
2
F36
I/O
OVDD
H34
I/O
OVDD
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Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal IRQ[4:5] IRQ[6]/ LCS[6]/ CKSTOP_OUT IRQ[7]/ LCS[7]/ CKSTOP_IN G33, G32 E35 Package Pin Number Pin Type I/O I/O Power Supply OVDD OVDD Notes
H36
I/O
OVDD
DUART UART1_SOUT/ M1SRCID[0]/ M2SRCID[0]/ LSRCID[0] UART1_SIN/ M1SRCID[1]/ M2SRCID[1]/ LSRCID[1] UART1_CTS/ M1SRCID[2]/ M2SRCID[2]/ LSRCID[2] UART1_RTS M1SRCID[3]/ M2SRCID[3]/ LSRCID[3] E32 O OVDD
B34
I/O
OVDD
C34
I/O
OVDD
A35
O
OVDD
I2C Interface IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL D34 B35 E33 C35 QUICCTM CE_PA[0] CE_PA[1:2] CE_PA[3:7] CE_PA[8] CE_PA[9:12] CE_PA[13:14] CE_PA[15] CE_PA[16] CE_PA[17:21] CE_PA[22] CE_PA[23:26] CE_PA[27:28] F8 AH1, AG5 F6, D4, C3, E5, A3 AG3 F7, B3, E6, B4 AG1, AF6 B2 AF4 B16, A16, E17, A17, B17 AF3 C18, D18, E18, A18 AF2, AE6 Engine I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LVDD0 OVDD LVDD0 OVDD LVDD0 OVDD LVDD0 OVDD LVDD1 OVDD LVDD1 OVDD I/O I/O I/O I/O OVDD OVDD OVDD OVDD 2 2 2 2
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 74 Freescale Semiconductor
Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal CE_PA[29] CE_PA[30] CE_PA[31] CE_PB[0:27] B19 AE5 F16 AE2, AE1, AD5, AD3, AD2, AC6, AC5, AC4, AC2, AC1, AB5, AB4, AB3, AB1, AA6, AA4, AA2, Y6, Y4, Y3, Y2, Y1, W6, W5, W2, V5, V3, V2 V1, U6 C16, A15 U4, U3, T6 C19 A4, C5 T5, T4, T2, T1, R5, R3, R1, C11, D12, F13, B10, C10, E12, A9, B8, D10, A14, E15, B14, D15, AH2 E11, D9, C8, F11, A7, E9, C7, A6, F10, B6, D7, E8, B5, A5, C2, E4, F5, B1, D2, G5, D1, E2, H6, F3, E1, F2, G3, H4 K3, J2, F1, G2, J5, H3, G1, H2, K6, J3, K5, K4, L6, P6, P4, P3, P1, N4, N5, N2, N1, M2, M3, M5, M6, L1, L2, L4, E14, C13, C14, B13 F14, D13, A12, A11 Clocks PCI_CLK_OUT[0]/ CE_PF[26] PCI_CLK_OUT[1:2]/ CE_PF[27:28] CLKIN PCI_CLOCK/ PCI_SYNC_IN PCI_SYNC_OUT/ CE_PF[29] B22 D22, A23 E37 M36 D37 JTAG TCK TDI TDO TMS TRST K33 K34 H37 J36 L32 Test TEST TEST_SEL L35 AU34 PMC QUIESCE B36 O OVDD I I OVDD GVDD 7 7 I I O I I OVDD OVDD OVDD OVDD OVDD 4 3 4 4 I/O I/O I I I/O LVDD2 OVDD OVDD OVDD OVDD 3 Package Pin Number Pin Type I/O I/O I/O I/O Power Supply LVDD1 OVDD LVDD1 OVDD Notes
CE_PC[0:1] CE_PC[2:3] CE_PC[4:6] CE_PC[7] CE_PC[8:9] CE_PC[10:30] CE_PD[0:27]
I/O I/O I/O I/O I/O I/O I/O
OVDD LVDD1 OVDD LVDD2 LVDD0 OVDD OVDD
CE_PE[0:31]
I/O
OVDD
CE_PF[0:3]
I/O
OVDD
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 75
Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal Package Pin Number System Control PORESET HRESET SRESET L37 L36 M33 Thermal Management THERM0 THERM1 AP19 AT31 Power and Ground Signals AVDD1 K35 Power for LBIU DLL (1.2 V) Power for CE PLL (1.2 V) Power for e300 PLL (1.2 V) Power for system PLL (1.2 V) -- AVDD1 I I GVDD GVDD I I/O I/O OVDD OVDD OVDD 1 2 Pin Type Power Supply Notes
AVDD2
K36
AVDD2
AVDD5
AM29
AVDD5
AVDD6
K37
AVDD6
GND
A2, A8, A13, A19, A22, A25, A31, A33, A36, B7, B12, B24, B27, B30, C4, C6, C9, C15, C26, C32, D3, D8, D11, D14, D17, D19, D23, D27, E7, E13, E25, E30, E36, F4, F37, G34, H1, H5, H32, H33, J4, J32, J37, K1, L3, L5, L33, L34, M1, M34, M35, N37, P2, P5, P35, P36, R4, T3, U1, U5, U35, V37, W1, W4, W33, W36, Y34, AA3, AA5, AC3, AC32, AC35, AD1, AD37, AE4, AE34, AE36, AF33, AG4, AG6, AG32, AH35, AJ1, AJ4, AJ32, AJ35, AJ37, AK36, AL3, AL34, AM4, AN6, AN23, AN30, AP8, AP12, AP14, AP16, AP17, AP20, AP25, AR6, AR8, AR9, AR19, AR24, AR31, AR35, AR37, AT4, AT10, AT19, AT20, AT25, AU14, AU22, AU28, AU35 AD4, AE3, AF1, AF5, AF35, AF37, AG2, AG36, AH33, AH34, AK5, AM1, AM35, AM37, AN2, AN10, AN11, AN12, AN14, AN32, AN36, AP5, AP23, AP28, AR1, AR7, AR10, AR12, AR21, AR25, AR27, AR33, AT15, AT22, AT28, AT33, AU2, AU5, AU16, AU31, AU36
--
GVDD
Power for DDR DRAM I/O Voltage (2.5 V or 1.8 V) Power for UCC1 Ethernet Interface (2.5V, 3.3V)
GVDD
LVDD0
D5, D6
LVDD0
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 76 Freescale Semiconductor
Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal LVDD1 C17, D16 Package Pin Number Pin Type Power for UCC2 Ethernet Interface option 1 (2.5V, 3.3V) Power for UCC2 Ethernet Interface Option 2 (2.5V, 3.3V) Power for Core (1.2 V) Power Supply LVDD1 Notes 9
LVDD2
B18, E21
LVDD2
9
VDD
C36, D29, D35, E16, F9, F12, F15, F17, F18, F20, F21, F23, F25, F26, F29, F31, F32, F33, G6, J6, K32, M32, N6, P33, R6, R32, U32, V6, Y5, Y32, AB6, AB33, AD6, AF32, AK6, AL6, AM7, AM9, AM10, AM11, AM12, AM13, AM14, AM15, AM18, AM21, AM25, AM28, AM32, AN15, AN21, AN26, AU9, AU17
VDD
OVDD
PCI, A10, B9, B15, B32, C1, C12, C22, C29, D24, E3, E10, 10/100 E27, G4, H35, J1, J35, K2, M4, N3, N34, R2, R37, T36, U2, U33, V4, V34, W3, Y35, Y37, AA1, AA36, AB2, AB34 Ethernet, and other Standard (3.3 V) AN20 I
OVDD
MVREF1
DDR Referenc e Voltage DDR Referenc e Voltage OVDD GVDD GVDD GVDD 8 7 8
MVREF2
AU32
I
SPARE1 SPARE3 SPARE4 SPARE5
B11 AH32 AU18 AP1 No Connect
I/O -- -- --
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 77
Package and Pin Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal NC AM20, AU19 Package Pin Number Pin Type -- Power Supply -- Notes --
Notes: 1. This pin is an open drain signal. A weak pull-up resistor (1 k) should be placed on this pin to OVDD 2. This pin is an open drain signal. A weak pull-up resistor (2-10 k) should be placed on this pin to OVDD. 3. This output is actively driven during reset rather than being three-stated during reset. 4. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 5.This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation. 6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance 7. This pin must always be tied to GND. 8. This pin must always be left not connected. 9. Refers to MPC8360E PowerQUICC IITM Pro Integrated Communications Processor Reference Manual section on "RGMII Pins" for information about the two UCC2 Ethernet interface options. 10. It is recommended that MDIC0 be tied to GND using an 18.2 resistor and MDIC1 be tied to DDR power using an 18.2 resistor for DDR2.
Table 67 shows the pin list of the MPC8358E TBGA package.
Table 67. MPC8358E TBGA Pinout Listing
Signal Package Pin Number DDR SDRAM Memory Controller Interface MEMC1_MDQ[0:63] AJ34, AK33, AL33, AL35, AJ33, AK34, AK32, AM36, AN37, AN35, AR34, AT34, AP37, AP36, AR36, AT35, AP34, AR32, AP32, AM31, AN33, AM34, AM33, AM30, AP31, AM27, AR30, AT32, AN29, AP29, AN27, AR29, AN8, AN7, AM8, AM6, AP9, AN9, AT7, AP7, AU6, AP6, AR4, AR3, AT6, AT5, AR5, AT3, AP4, AM5, AP3, AN3, AN5, AL5, AN4, AM2, AL2, AH5, AK3, AJ2, AJ3, AH4, AK4, AH3 AP24, AN22, AM19, AN19, AM24 AM23 AM22, AN18 AL36, AN34, AP33, AN28,AT9, AU4, AM3, AJ6,AP27 AK35, AP35, AN31, AM26,AT8, AU3, AL4, AJ5, AP26 AU29, AU30 AT30 AU21, AP22, AP21, AT21, AU25, AU26, AT23, AR26, AU24, AR23, AR28, AU23, AR22, AU20, AR18 AG33, AJ36, AT1, AK2 AT26 AT29 AT24 I/O GVDD Pin Type Power Supply Notes
MEMC_MECC[0:4]/ MSRCID[0:4] MEMC_MECC[5]/ MDVAL MEMC_MECC[6:7] MEMC_MDM[0:8] MEMC_MDQS[0:8] MEMC_MBA[0:1] MEMC_MBA[2] MEMC_MA[0:14] MEMC_MODT[0:3] MEMC_MWE MEMC_MRAS MEMC_MCAS
I/O I/O I/O O I/O O O O O O O O
GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD 6
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 78 Freescale Semiconductor
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal MEMC_MCS[0:3] MEMC_MCKE[0:1] MEMC_MCK[0:5] MEMC_MCK[0:5] MDIC[0:1] Package Pin Number AU27, AT27, AU8, AU7 AL32, AU33 AK37, AT37, AN1, AR2, AN25, AK1 AL37, AT36, AP2, AT2, AN24, AL1 AH6, AP30 PCI PCI_INTA/ IRQ_OUT/ CE_PF[5] PCI_RESET_OUT/ CE_PF[6] PCI_AD[31:30]/ CE_PG[31:30] PCI_AD[29:25]/ CE_PG[29:25] PCI_AD[24]/ CE_PG[24] PCI_AD[23:0]/ CE_PG[23:0] PCI_C/ BE[3:0]/ CE_PF[10:7] PCI_PAR/ CE_PF[11] PCI_FRAME/ CE_PF[12] PCI_TRDY/ CE_PF[13] PCI_IRDY/ CE_PF[14] PCI_STOP/ CE_PF[15] PCI_DEVSEL/ CE_PF[16] PCI_IDSEL/ CE_PF[17] PCI_SERR/ CE_PF[18] PCI_PERR/ CE_PF[19] PCI_REQ[0]/ CE_PF[20] A20 I/O LVDD2 2 Pin Type O O O O I/O Power Supply GVDD GVDD GVDD GVDD GVDD 11 3 Notes
E19 D20, D21 A24, B23, C23, E23, A26 B21 C24, C25, D25, B25, E24, F24, A27, A28, F27, A30, C30, D30, E29, B31, C31, D31, D32, A32, C33, B33, F30, E31, A34, D33 E22, B26, E28, F28
I/O I/O I/O I/O I/O
LVDD2 LVDD2 OVDD LVDD2 OVDD
I/O
OVDD
D28 D26 C27 C28 B28 E26 F22 B29 A29 F19
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD LVDD2 5 5 5 5 5 5 5
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 79
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal PCI_REQ[1]/ CPCI_HS_ES/ CE_PF[21] PCI_REQ[2]/ CE_PF[22] PCI_GNT[0]/ CE_PF[23] PCI_GNT[1]/ CPCI1_HS_LED/ CE_PF[24] PCI_GNT[2]/ CPCI1_HS_ENUM/ CE_PF[25] PCI_MODE M66EN/CE_PF[4] A21 Package Pin Number Pin Type I/O Power Supply LVDD2 Notes
C21 E20 B20
I/O I/O I/O
LVDD2 LVDD2 LVDD2
C20
I/O
LVDD2
D36 B37 Local Bus Controller Interface
I I/O
OVDD OVDD
LAD[0:31]
N32, N33, N35, N36, P37, P32, P34, R36, R35, R34, R33, T37, T35, T34, T33, U37, T32, U36, U34, V36, V35, W37, W35, V33, V32, W34, Y36, W32, AA37, Y33, AA35, AA34 AB37 AB36 AB35 AA33 AC37, AA32, AC36, AC34, AD36 AD33, AG37, AF34, AE33, AD32, AH37 AG35, AG34, AH36, AE32
I/O
OVDD
LDP[0]/ CKSTOP_OUT LDP[1]/ CKSTOP_IN LDP[2]/ LCS[6] LDP[3]/ LCS[7] LA[27:31] LCS[0:5] LWE[0:3]/ LSDDQM[0:3]/ LBS[0:3] LBCTL LALE LGPL0/ LSDA10/ cfg_reset_source0 LGPL1/ LSDWE/ cfg_reset_source1 LGPL2/ LSDRAS/ LOE
I/O I/O I/O I/O O O O
OVDD OVDD OVDD OVDD OVDD OVDD OVDD
AD35 M37 AB32
O O I/O
OVDD OVDD OVDD
AE37
I/O
OVDD
AC33
O
OVDD
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 80 Freescale Semiconductor
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal LGPL3/ LSDCAS/ cfg_reset_source2 LGPL4/ LGTA/ LUPWAIT/ LPBSE LGPL5/ cfg_clkin_div LCKE LCLK[0] LCLK[1]/ LCS[6] LCLK[2]/ LCS[7] LSYNC_OUT LSYNC_IN AD34 Package Pin Number Pin Type I/O Power Supply OVDD Notes
AE35
I/O
OVDD
AF36 G36 J33 J34 G37 F34 G35 Programmable Interrupt Controller
I/O O O O O O I
OVDD OVDD OVDD OVDD OVDD OVDD OVDD
MCP_OUT IRQ0/ MCP_IN IRQ[1]/ M1SRCID[4]/ M2SRCID[4]/ LSRCID[4] IRQ[2]/ M1DVAL/ M2DVAL/ LDVAL IRQ[3]/ CORE_SRESET IRQ[4:5] IRQ[6]/ LCS[6]/ CKSTOP_OUT IRQ[7]/ LCS[7]/ CKSTOP_IN
E34 C37 F35
O I I/O
OVDD OVDD OVDD
2
F36
I/O
OVDD
H34 G33, G32 E35
I/O I/O I/O
OVDD OVDD OVDD
H36
I/O
OVDD
DUART UART1_SOUT/ M1SRCID[0]/ M2SRCID[0]/ LSRCID[0] E32 O OVDD
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 81
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal UART1_SIN/ M1SRCID[1]/ M2SRCID[1]/ LSRCID[1] UART1_CTS/ M1SRCID[2]/ M2SRCID[2]/ LSRCID[2] UART1_RTS/ M1SRCID[3]/ M2SRCID[3]/ LSRCID[3] B34 Package Pin Number Pin Type I/O Power Supply OVDD Notes
C34
I/O
OVDD
A35
O
OVDD
I2C Interface IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL D34 B35 E33 C35 QUICCTM CE_PA[0] CE_PA[1:2] CE_PA[3:7] CE_PA[8] CE_PA[9:12] CE_PA[13:14] CE_PA[15] CE_PA[16] CE_PA[17:21] CE_PA[22] CE_PA[23:26] CE_PA[27:28] CE_PA[29] CE_PA[30] CE_PA[31] CE_PB[0:27] F8 AH1, AG5 F6, D4, C3, E5, A3 AG3 F7, B3, E6, B4 AG1, AF6 B2 AF4 B16, A16, E17, A17, B17 AF3 C18, D18, E18, A18 AF2, AE6 B19 AE5 F16 AE2, AE1, AD5, AD3, AD2, AC6, AC5, AC4, AC2, AC1, AB5, AB4, AB3, AB1, AA6, AA4, AA2, Y6, Y4, Y3, Y2, Y1, W6, W5, W2, V5, V3, V2 V1, U6 C16, A15 U4, U3, T6 C19 A4, C5 Engine I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LVDD0 OVDD LVDD0 OVDD LVDD0 OVDD LVDD0 OVDD LVDD1 OVDD LVDD1 OVDD LVDD1 OVDD LVDD1 OVDD I/O I/O I/O I/O OVDD OVDD OVDD OVDD 2 2 2 2
CE_PC[0:1] CE_PC[2:3] CE_PC[4:6] CE_PC[7] CE_PC[8:9]
I/O I/O I/O I/O I/O
OVDD LVDD1 OVDD LVDD2 LVDD0
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 82 Freescale Semiconductor
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal CE_PC[10:30] CE_PD[0:27] Package Pin Number T5, T4, T2, T1, R5, R3, R1, C11, D12, F13, B10, C10, E12, A9, B8, D10, A14, E15, B14, D15, AH2 E11, D9, C8, F11, A7, E9, C7, A6, F10, B6, D7, E8, B5, A5, C2, E4, F5, B1, D2, G5, D1, E2, H6, F3, E1, F2, G3, H4 K3, J2, F1, G2, J5, H3, G1, H2, K6, J3, K5, K4, L6, P6, P4, P3, P1, N4, N5, N2, N1, M2, M3, M5, M6, L1, L2, L4, E14, C13, C14, B13 F14, D13, A12, A11 Clocks PCI_CLK_OUT[0]/ CE_PF[26] PCI_CLK_OUT[1:2]/ CE_PF[27:28] CLKIN PCI_CLOCK/ PCI_SYNC_IN PCI_SYNC_OUT/ CE_PF[29] B22 D22, A23 E37 M36 D37 JTAG TCK TDI TDO TMS TRST K33 K34 H37 J36 L32 Test TEST TEST_SEL L35 AU34 PMC QUIESCE B36 System Control PORESET HRESET SRESET L37 L36 M33 Thermal Management THERM0 THERM1 AP19 AT31 I I GVDD GVDD I I/O I/O OVDD OVDD OVDD 1 2 O OVDD I I OVDD GVDD 7 10 I I O I I OVDD OVDD OVDD OVDD OVDD 4 3 4 4 I/O I/O I I I/O LVDD2 OVDD OVDD OVDD OVDD 3 Pin Type I/O I/O Power Supply OVDD OVDD Notes
CE_PE[0:31]
I/O
OVDD
CE_PF[0:3]
I/O
OVDD
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 83
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal Package Pin Number Power and Ground Signals AVDD1 K35 Power for LBIU DLL (1.2 V) Power for CE PLL (1.2 V) Power for e300 PLL (1.2 V) Power for system PLL (1.2 V) -- AVDD1 Pin Type Power Supply Notes
AVDD2
K36
AVDD2
AVDD5
AM29
AVDD5
AVDD6
K37
AVDD6
GND
A2, A8, A13, A19, A22, A25, A31, A33, A36, B7, B12, B24, B27, B30, C4, C6, C9, C15, C26, C32, D3, D8, D11, D14, D17, D19, D23, D27, E7, E13, E25, E30, E36, F4, F37, G34, H1, H5, H32, H33, J4, J32, J37, K1, L3, L5, L33, L34, M1, M34, M35, N37, P2, P5, P35, P36, R4, T3, U1, U5, U35, V37, W1, W4, W33, W36, Y34, AA3, AA5, AC3, AC32, AC35, AD1, AD37, AE4, AE34, AE36, AF33, AG4, AG6, AG32, AH35, AJ1, AJ4, AJ32, AJ35, AJ37, AK36, AL3, AL34, AM4, AN6, AN23, AN30, AP8, AP12, AP14, AP16, AP17, AP20, AP25, AR6, AR8, AR9, AR19, AR24, AR31, AR35, AR37, AT4, AT10, AT19, AT20, AT25, AU14, AU22, AU28, AU35 AD4, AE3, AF1, AF5, AF35, AF37, AG2, AG36, AH33, AH34, AK5, AM1, AM35, AM37, AN2, AN10, AN11, AN12, AN14, AN32, AN36, AP5, AP23, AP28, AR1, AR7, AR10, AR12, AR21, AR25, AR27, AR33, AT15, AT22, AT28, AT33, AU2, AU5, AU16, AU31, AU36
--
GVDD
Power for DDR DRAM I/O Voltage (2.5 V or 1.8 V) Power for UCC1 Ethernet Interface (2.5V, 3.3V) Power for UCC2 Ethernet Interface option 1 (2.5V, 3.3V)
GVDD
LVDD0
D5, D6
LVDD0
LVDD1
C17, D16
LVDD1
9
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 84 Freescale Semiconductor
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal LVDD2 B18, E21 Package Pin Number Pin Type Power for UCC2 Ethernet Interface Option 2 (2.5V, 3.3V) Power for Core (1.2 V) Power Supply LVDD2 Notes 9
VDD
C36, D29, D35, E16, F9, F12, F15, F17, F18, F20, F21, F23, F25, F26, F29, F31, F32, F33, G6, J6, K32, M32, N6, P33, R6, R32, U32, V6, Y5, Y32, AB6, AB33, AD6, AF32, AK6, AL6, AM7, AM9, AM10, AM11, AM12, AM13, AM14, AM15, AM18, AM21, AM25, AM28, AM32, AN15, AN21, AN26, AU9, AU17
VDD
OVDD
PCI, A10, B9, B15, B32, C1, C12, C22, C29, D24, E3, E10, 10/100 E27, G4, H35, J1, J35, K2, M4, N3, N34, R2, R37, T36, U2, U33, V4, V34, W3, Y35, Y37, AA1, AA36, AB2, AB34 Ethernet, and other Standard (3.3 V) AN20 I
OVDD
MVREF1
DDR Referenc e Voltage DDR Referenc e Voltage OVDD GVDD GVDD GVDD 8 7 8
MVREF2
AU32
I
SPARE1 SPARE3 SPARE4 SPARE5
B11 AH32 AU18 AP1 No Connect
I/O -- -- --
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 85
Package and Pin Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal NC Package Pin Number AM16, AM17, AM20, AN13, AN16, AN17, AP10, AP11, AP13, AP15, AP18, AR11, AR13, AR14, AR15, AR16, AR17, AR20, AT11, AT12, AT13, AT14, AT16, AT17, AT18, AU10, AU11, AU12, AU13, AU15, AU19 Pin Type -- Power Supply -- Notes --
Notes: 1. This pin is an open drain signal. A weak pull-up resistor (1 k) should be placed on this pin to OVDD. 2. This pin is an open drain signal. A weak pull-up resistor (2-10 k) should be placed on this pin to OVDD. 3. This output is actively driven during reset rather than being three-stated during reset. 4. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation. 6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance. 7. This pin must always be tied to GND. 8. This pin must always be left not connected. 9. Refers to MPC8360E PowerQUICC IITM Pro Integrated Communications Processor Reference Manual section on "RGMII Pins" for information about the two UCC2 Ethernet interface options. 10. This pin must always be tied to GVDD. 11. It is recommended that MDIC0 be tied to GND using an 18.2 resistor and MDIC1 be tied to DDR power using an 18.2 resistor for DDR2.
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22 Clocking
Figure 53 shows the internal distribution of clocks within the MPC8360E.
MPC8360E e300 core Core PLL core_clk
csb_clk ce_clk to QUICC Engine block DDRC1 /2 ddr1_clk QUICC Engine PLL DDRC2 System PLL Clock Unit lb_clk /n to local bus/ DDRC2 LBIU controller DLL csb_clk to rest of the device CFG_CLKIN_DIV CLKIN PCI Clock Divider PCI_CLK_OUT[0:2] /2 MEMC2_MCK[0:1] MEMC2_MCK[0:1] DDRC2 Memory Device DDRC1 Memory Device
MEMC1_MCK[0:5] MEMC1_MCK[0:5]
LCLK[0:2] LSYNC_OUT LSYNC_IN PCI_CLK/ PCI_SYNC_IN Local Bus Memory Device
PCI_SYNC_OUT
Figure 53. MPC8360E Clock Subsystem
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Figure 54 shows the internal distribution of clocks within the MPC8358E.
MPC8358E e300 core Core PLL core_clk
csb_clk ce_clk to QUICC Engine block DDRC /2 ddr1_clk QUICC Engine PLL Clock Unit lb_clk /n LBIU DLL csb_clk to rest of the device CFG_CLKIN_DIV CLKIN PCI Clock Divider PCI_CLK_OUT[0:2] LCLK[0:2] LSYNC_OUT LSYNC_IN PCI_CLK/ PCI_SYNC_IN Local Bus Memory Device DDRC Memory Device
MEMC1_MCK[0:5] MEMC1_MCK[0:5]
System PLL
PCI_SYNC_OUT
Figure 54. MPC8358E Clock Subsystem
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Note that in PCI host mode, the primary clock input also depends on whether PCI clock outputs are selected with RCWH[PCICKEN]. When the device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is selected (RCWH[PCICKEN] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (/2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.The OCCR[PCIOENn] parameters enable the PCI_CLK_OUTn respectively.
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PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system, to allow the device to function. When the device is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured as a PCI agent device the CLKIN and the CFG_CLKIN_DIV signals should be tied to GND. When the device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is disabled (RCWH[PCICKEN] = 0), clock distribution and balancing done externally on the board. Therefore, PCI_SYNC_IN is the primary input clock. As shown in Figure 53, the primary clock input (frequency) is multiplied by the QUICC Engine block phase-locked loop (PLL), the system PLL, and the clock unit to create the QUICC Engine clock (ce_clk), the coherent system bus clock (csb_clk), the internal DDRC1 controller clock (ddr1_clk), and the internal clock for the local bus interface unit and DDR2 memory controller (lb_clk). The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = {PCI_SYNC_IN x (1 + CFG_CLKIN_DIV)} x SPMF In PCI host mode, PCI_SYNC_IN x (1 + CFG_CLKIN_DIV) is the CLKIN frequency; in PCI agent mode, CFG_CLKIN_DIV must be pulled down (low), so PCI_SYNC_IN x (1 + CFG_CLKIN_DIV) is the PCI_CLK frequency. The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, "Reset, Clocking, and Initialization," in the MPC8360E Integrated Communications Processor Reference Manual, Rev. 2 for more information on the clock subsystem. The ce_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF) and the QUICC Engine PLL division factor (RCWL[CEPDF]) according to the following equation: ce_clk = (primary clock input x CEPMF) / (1 + CEPDF) The internal ddr1_clk frequency is determined by the following equation: ddr1_clk = csb_clk x (1 + RCWL[DDR1CM]) Note that the lb_clk clock frequency (for DDRC2) is determined by RCWL[LBCM]. The internal ddr1_clk frequency is not the external memory bus frequency; ddr1_clk passes through the DDRC1 clock divider (/2) to create the differential DDRC1 memory bus clock outputs (MEMC1_MCK and MEMC1_MCK). However, the data rate is the same frequency as ddr1_clk. The internal lb_clk frequency is determined by the following equation: lb_clk = csb_clk x (1 + RCWL[LBCM]) Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock divider ratio is controlled by LCCR[CLKDIV].
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In addition, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. Table 68 specifies which units have a configurable clock frequency.
Table 68. Configurable Clock Units
Unit Security Core PCI and DMA complex
1
Default Frequency
Options Off, csb_clk 1, csb_clk/2, csb_clk/3 Off, csb_clk
csb_clk/3
csb_clk
with limitation, only for slow csb_clk rates, up to 166MHz
Table 69 provides the operating frequencies for the TBGA package under recommended operating conditions (see Table 2). All frequency combinations shown in the table below may not be available. Maximum operating frequencies depend on the part ordered, see Section 26.1, "Part Numbers Fully Addressed by this Document" for part ordering details and contact your Freescale Sales Representative or authorized distributor for more information.
Table 69. Operating Frequencies for the TBGA Package
Characteristic 1 e300 core frequency (core_clk) Coherent system bus frequency (csb_clk) QUICC Engine frequency 3 (ce_clk) DDR and DDR2 memory bus frequency (MCLK) 4 Local bus frequency (LCLKn) 5 PCI input frequency (CLKIN or PCI_CLK) Security core maximum internal operating frequency
1 2 3 4 5
400 MHz 266-400
533 MHz 266-533 133-333
667 MHz 2 266-667
Unit MHz MHz
266-500
MHz
100-166.67
MHz
16.67-133
MHz
25-66.67 133 133 166
MHz MHz
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk, MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The 667 MHz core frequency is based on a 1.3 V VDD supply voltage. The 500 MHz QE frequency is based on a 1.3 V VDD supply voltage. The DDR data rate is 2x the DDR memory bus frequency. The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the csb_clk frequency (depending on RCWL[LBCM]).
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22.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters. Table 70 shows the multiplication factor encodings for the system PLL.
Table 70. System PLL Multiplication Factors
RCWL[SPMF] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 System PLL Multiplication Factor x 16 Reserved x2 x3 x4 x5 x6 x7 x8 x9 x 10 x 11 x 12 x 13 x 14 x 15
The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 71.
Table 71. System PLL VCO Divider
RCWL[SVCOD] 00 01 10 11 VCO Divider 4 8 2 Reserved
NOTE
The VCO divider must be set properly so that the system VCO frequency is in the range of 600-1400 MHz. The system VCO frequency is derived from the following equations: csb_clk = {PCI_SYNC_IN x (1 + CFG_CLKIN_DIV)} x SPMF
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System VCO Frequency = csb_clk x VCO divider As described in Section 22, "Clocking," the LBCM, DDRCM, and SPMF parameters in the reset configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 72 shows the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios.
Table 72. CSB Frequency Options
Input Clock Frequency (MHz)2 CFG_CLKIN_DIV at reset 1 SPMF
csb_clk : Input Clock Ratio 2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10 : 1 11 : 1 12 : 1 13 : 1 14 : 1 15 : 1 16 : 1 100 116 133 150 166 183 200 216 233 250 266 100 125 150 175 200 225 250 275 300 325 100 133 166 200 233 266 300 333 133 200 266 333
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Table 72. CSB Frequency Options (continued)
Input Clock Frequency (MHz)2 CFG_CLKIN_DIV at reset 1 SPMF
csb_clk : Input Clock Ratio 2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
High High High High High High High High High High High High High High High
1
0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000
2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10 : 1 11 : 1 12 : 1 13 : 1 14 : 1 15 : 1 16 : 1 100 133 166 200 233
133 200 266 333
CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be pulled down (low) in agent mode. 2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
22.2
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 73 shows the encodings for RCWL[COREPLL]. COREPLL values not listed in Table 73 should be considered reserved.
Table 73. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
0-1 nn 2-5 0000 6 n PLL bypassed (PLL off, csb_clk clocks core directly) 1:1 1:1
VCO divider
PLL bypassed (PLL off, csb_clk clocks core directly)
00 01
0001 0001
0 0
/2 /4
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Table 73. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
core_clk : csb_clk Ratio
0-1 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 2-5 0001 0001 0001 0001 0001 0001 0010 0010 0010 0010 0010 0010 0010 0010 0011 0011 0011 0011 6 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1:1 1:1 1.5:1 1.5:1 1.5:1 1.5:1 2:1 2:1 2:1 2:1 2.5:1 2.5:1 2.5:1 2.5:1 3:1 3:1 3:1 3:1
VCO divider
/8 /8 /2 /4 /8 /8 /2 /4 /8 /8 /2 /4 /8 /8 /2 /4 /8 /8
NOTE
Core VCO frequency = Core frequency x VCO divider. VCO divider (RCWL[COREPLL[0:1]]) must be set properly so that the core VCO frequency is in the range of 800-1800 MHz. Having a core frequency below the CSB frequency is not a possible option because the core frequency must be equal to or greater than the CSB frequency.
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22.3
QUICC Engine PLL Configuration
The QUICC Engine PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and RCWL[CEVCOD] parameters. Table 74 shows the multiplication factor encodings for the QUICC Engine PLL.
Table 74. QUICC Engine PLL Multiplication Factors
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF] / (1+RCWL[CEPDF]) x 16 Reserved x2 x3 x4 x5 x6 x7 x8 x9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 x 17 x 18 x 19 x 20 x 21 x 22 x 23 x 24 x 25 x 26 x 27
RCWL[CEPMF]
RCWL[CEPDF]
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 74. QUICC Engine PLL Multiplication Factors (continued)
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF] / (1+RCWL[CEPDF]) x 28 x 29 x 30 x 31 x 1.5 x 2.5 x 3.5 x 4.5 x 5.5 x 6.5 x 7.5 x 8.5 x 9.5 x 10.5 x 11.5 x 12.5 x 13.5 x 14.5
RCWL[CEPMF]
RCWL[CEPDF]
11100 11101 11110 11111 00011 00101 00111 01001 01011 01101 01111 10001 10011 10101 10111 11001 11011 11101 Notes 1. Reserved modes are not listed.
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
The RCWL[CEVCOD] denotes the QE PLL VCO internal frequency as shown in Table 75.
Table 75. QE PLL VCO Divider
RCWL[CEVCOD] 00 01 10 11 VCO Divider 4 8 2 Reserved
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NOTE
The VCO divider (RCWL[CEVCOD]) must be set properly so that the QE VCO frequency is in the range of 600-1400 MHz. The QE frequency is not restricted by the CSB and core frequencies. The CSB, core, and QE frequencies should be selected according to the performance requirements. The QE VCO frequency is derived from the following equations: ce_clk = (primary clock input x CEPMF) / (1 + CEPDF) QE VCO Frequency = ce_clk x VCO divider x (1 + CEPDF)
22.4
Suggested PLL Configurations
To simplify the PLL configurations, the device might be separated into two clock domains. The first domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock domains are independent, and each of their PLLs are configured separately. Both of the domains has one common input clock. Table 76 shows suggested PLL configurations for 33 MHz and 66 MHz input clocks and illustrates each of the clock domains separately. Any combination of clock domains setting with same input clock are valid. Refer to Section 22, "Clocking," for the appropriate operating frequencies for your device.
Table 76. Suggested PLL Configurations
Conf No. 1 CORE PLL Input CSB Freq Core Freq Clock Freq (MHz) (MHz) (MHz) QUICC Engine Freq (MHz) 400 533 667 (MHz) (MHz) (MHz)
SPMF
CEPMF
CEPDF
33 MHz CLKIN / PCI_SYNC_IN Options s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 0100 0100 0101 0101 0110 0110 0111 0111 0111 1000 1000 1000 1001 1001 1001 0000100 0000101 0000100 0000101 0000100 0000110 0000011 0000100 0000101 0000011 0000100 0000101 0000010 0000011 0000100 ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae ae 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 133 133 166 166 200 200 233 233 233 266 266 266 300 300 300 266 333 333 416 400 600 350 466 583 400 533 667 300 450 600
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Table 76. Suggested PLL Configurations (continued)
Conf No. 1 s16 s17 s18 c1 c2 c3 c4 c5 c6 CORE PLL 0000010 0000011 0000100 ae ae ae ae ae ae Input CSB Freq Core Freq Clock Freq (MHz) (MHz) (MHz) 33 33 33 33 33 33 33 33 33 333 333 333 333 500 667 300 400 466 500 533 566 QUICC Engine Freq (MHz) 400 533 667 (MHz) (MHz) (MHz)
SPMF
CEPMF
CEPDF
1010 1010 1010 ae ae ae ae ae ae
ae ae ae 01001 01100 01110 01111 10000 10001
ae ae ae 0 0 0 0 0 0
66 MHz CLKIN / PCI_SYNC_IN Options s1h s2h s3h s4h s5h s6h s7h s8h s9h c1h c2h c3h c4h c5h
1
0011 0011 0011 0100 0100 0100 0101 0101 0101 ae ae ae ae ae
0000110 0000101 0000110 0000011 0000100 0000101 0000010 0000011 0000100 ae ae ae ae ae
ae ae ae ae ae ae ae ae ae 00101 00110 00111 01000 01001
ae ae ae ae ae ae ae ae ae 0 0 0 0 0
66 66 66 66 66 66 66 66 66 66 66 66 66 66
200 200 200 266 266 266 333 333 333
400 500 600 400 533 667 333 500 667 333 400 466 533 600

The Conf No. consist of prefix, an index and a postfix. The prefix `s' and `c' stands for `syset' and `ce' respectively. the postfix `h' stands for `high input clock.' The index is a serial number.
The following steps describe how to use Table 76. See the example that follows: 1. Choose the up or down sections in the table according to input clock rate 33 MHz or 66 MHz. 2. Select a suitable CSB and core clock rates from Table 76. Copy the SPMF and CORE PLL configuration bits. 3. Select a suitable QUICC Engine clock rate from Table 76. Copy the CEPMF and CEPDF configuration bits.
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4. Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields respectively. Example:
Index SPMF CORE PLL 0000011 0000100 CEPMF CEPDF QUICC 400 533 667 Input Clock CSB Freq Core Freq Engine Freq (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) 33 66 266 266 400 533 300 400
A B
1000 0100
01001 00110
0 0
*
*
Example A. To configure the device with CSB clock rate of 266 MHz, core rate of 400 MHz, and QUICC Engine clock rate 300 MHz while the input clock rate is 33 MHz. Conf No. "s10" and "c1" are selected from Table 76. SPMF is "1000," CORPLL is "0000011," CEPMF is "01001," and CEPDF is "0." Example B. To configure the device with CSBCSB clock rate of 266 MHz, core rate of 533 MHz and QUICC Engine clock rate 400 MHz while the input clock rate is 66 MHz. Conf No. "s5h" and "c2h" are selected from Table 76. SPMF is "0100," CORPLL is "0000100," CEPMF is "00110" and CEPDF is "0."
23 Thermal
This section describes the thermal specifications of the MPC8360E/58E.
23.1
Thermal Characteristics
Table 77. Package Thermal Characteristics for the TBGA Package
Characteristic Symbol RJA RJA RJMA RJMA RJMA RJMA RJB RJC Value 15 11 10 8 9 7 4.5 1.1 Unit C/W C/W C/W C/W C/W C/W C/W C/W Notes 1, 2 1, 3 1, 3 1, 3 1, 3 1, 3 4 5
Table 77 provides the package thermal characteristics for the 740 37.5 mm x 37.5 mm TBGA package.
Junction-to-ambient Natural Convection on single layer board (1s) Junction-to-ambient Natural Convection on four layer board (2s2p) Junction-to-ambient (@1 m/s) on single layer board (1s) Junction-to-ambient (@ 1 m/s) on four layer board (2s2p) Junction-to-ambient (@ 2 m/s) on single layer board (1s) Junction-to-ambient (@ 2 m/s) on four layer board (2s2p) Junction-to-board thermal Junction-to-case thermal
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Table 77. Package Thermal Characteristics for the TBGA Package (continued)
Characteristic Junction-to-Package Natural Convection on Top Symbol JT Value 1 Unit C/W Notes 6
Notes 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 and SEMI G38-87with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 1 m/sec is approximately equal to 200 linear feet per minute (LFM). 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
23.2
Thermal Management Information
For the following sections, PD = (VDD X IDD) + PI/O where PI/O is the power dissipation of the I/O drivers. See Table 6 for typical power dissipations values.
23.2.1
Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance
An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA x PD) where: TJ = junction temperature (C) TA = ambient temperature for the package (C) RJA = junction to ambient thermal resistance (C/W) PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. As a general statement, the value obtained on a single layer board is appropriate for a tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ - TA) are possible.
23.2.2
Estimation of Junction Temperature with Junction-to-Board Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For
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many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package will be approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RJB x PD) where: TJ = junction temperature (C) TB = board temperature at the package perimeter (C) RJA = junction to board thermal resistance (C/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes.
23.2.3
Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TJ = junction temperature (C) TT = thermocouple temperature on top of package (C) JT = junction to ambient thermal resistance (C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
23.2.4
Heat Sinks and Junction-to-Case Thermal Resistance
In some application environments, a heat sink will be required to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RJA = RJC + RCA where:
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RJA = junction to ambient thermal resistance (C/W) RJC = junction to case thermal resistance (C/W) RCA = case to ambient thermal resistance (C/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. Table 78 shows heat sinks and junction-to-case thermal resistance for TBGA package.
Table 78. Heat Sinks and Junction-to-Case Thermal Resistance of TBGA Package
35x35 mm TBGA Heat Sink Assuming Thermal Grease Air Flow Junction-to-Ambient Thermal Resistance 10.7 6.2 5.3 8.1 4.4 3.7 5.4 3.2 2.4 6.4 3.8 2.5 2.8
AAVID 30x30x9.4 mm Pin Fin AAVID 30x30x9.4 mm Pin Fin AAVID 30x30x9.4 mm Pin Fin AAVID 31x35x23 mm Pin Fin AAVID 31x35x23 mm Pin Fin AAVID 31x35x23 mm Pin Fin Wakefield, 53x53x25 mm Pin Fin Wakefield, 53x53x25 mm Pin Fin Wakefield, 53x53x25 mm Pin Fin MEI, 75x85x12 no adjacent board, extrusion MEI, 75x85x12 no adjacent board, extrusion MEI, 75x85x12 no adjacent board, extrusion MEI, 75x85x12 mm, adjacent board, 40 mm Side bypass
Natural Convention 1 m/s 2 m/s Natural Convention 1 m/s 2 m/s Natural Convention 1 m/s 2 m/s Natural Convention 1 m/s 2 m/s 1 m/s
Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request.
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 102 Freescale Semiconductor
Thermal
Heat sink vendors include the following:
Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 473 Sapena Ct. #15 Santa Clara, CA 95054 Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Millennium Electronics (MEI) Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-millennium.com Tyco Electronics Chip CoolersTM P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com 603-224-9988
408-749-7601
818-842-7277
408-436-8770
800-522-6752
603-635-5102
Interface material vendors include the following:
Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01888-4014 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com 781-935-4850
800-248-2481
888-642-7674
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 103
System Design Information
The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com
800-347-4572
23.3
Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. Recommended maximum force on the top of the package is 10 lb force (4.5 kg force). If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance verified under the application requirements.
23.3.1
Experimental Determination of the Junction Temperature with a Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction to case thermal resistance. TJ = TC + (RJC x PD) where: TJ = junction temperature (C) TC = case temperature of the package (C) RJC = junction to case thermal resistance (C/W) PD = power dissipation (W)
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of the MPC8360E/58E. Additional information can be found in AN3097, MPC8360E/MPC8358E PowerQUICCTM Design Checklist, Rev. 1.
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 104 Freescale Semiconductor
System Design Information
24.1
System Clocking
The device includes two PLLs. 1. The platform PLL (AVDD1) generates the platform clock from the externally supplied CLKIN input. The frequency ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in Section 22.1, "System PLL Configuration." 2. The e300 core PLL (AVDD2) generates the core clock as a slave to the platform clock. The frequency ratio between the e300 core clock and the platform clock is selected using the e300 PLL ratio configuration bits as described in Section 22.2, "Core PLL Configuration."
24.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1, AVDD2 respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD through a low frequency filter scheme such as the following. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide five independent filter circuits as illustrated in Figure 55, one to each of the five AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package, without the inductance of vias. Figure 55 shows the PLL power supply filter circuit.
10 V DD 2.2 F 2.2 F Low ESL Surface Mount Capacitors AVDDn
GND
Figure 55. PLL Power Supply Filter Circuit
24.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the device system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the device. These decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 105
System Design Information
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors--100-330 F (AVX TPS tantalum or Sanyo OSCON).
24.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of the device.
24.5
Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 56). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 106 Freescale Semiconductor
System Design Information
OV DD
RN
SW2 Data Pad SW1
RP
OGND
Figure 56. Driver Impedance Measurement
The value of this resistance and the strength of the driver's current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource x Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value Rterm. The measured voltage is V2 = 1/(1/R1 + 1/R2)) x Isource. Solving for the output impedance gives Rsource = Rterm x (V1/V2 - 1). The drive current is then Isource = V1/Rsource. Table 79 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal OVDD, 105C.
Table 79. Impedance Characteristics
Local Bus, Ethernet, DUART, Control, Configuration, Power Management 42 Target 42 Target NA
Impedance
PCI
DDR DRAM
Symbol
Unit
RN RP Differential
25 Target 25 Target NA
20 Target 20 Target NA
Z0 Z0 ZDIFF
W W W
Note: Nominal supply voltages. See Table 1, TJ = 105C.
24.6
Configuration Pin Muxing
The device provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 107
Document Revision History
and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured.
24.7
Pull-Up Resistor Requirements
The device requires high resistance pull-up resistors (10 k is recommended) on open drain type pins including I2C pins, Ethernet Management MDIO pin, and EPIC interrupt pins. For more information on required pull-up resistors and the connections required for the JTAG interface, see AN3097, MPC8360E/MPC8358E PowerQUICCTM Design Checklist, Rev. 1.
25 Document Revision History
Table 80 provides a revision history for this hardware specification.
Table 80. Document Revision History
Rev. Number 0 Date 12/07/2007 Initial release. Substantive Change(s)
26 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 26.1, "Part Numbers Fully Addressed by this Document."
26.1
Part Numbers Fully Addressed by this Document
Table 81 provides the Freescale part numbering nomenclature for the MPC8360E/58E. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number.
MPC8360E/MPC8358E PowerQUICCTM II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 108 Freescale Semiconductor
Ordering Information
Table 81. Part Numbering Nomenclature 1
MPC nnnn e t pp aa
Processor Frequency 3
a
Platform Frequency
a
QUICC Engine Frequency
A
Die Revision A=revision 2.1 silicon
Product Part Encryption Temperature Package 2 Code Identifier Acceleration Range MPC 8358 Blank = Not included E = included 0C TA to 105C TJ
D = 266 MHz E = 300 MHz ZU = TBGA e300 G = 400 MHz core speed VV = TBGA AD = 266 MHz (no lead) AG = 400 MHz D = 266 MHz G = 400 MHz e300 F = 333 MHz H = 500 MHz core speed AG = 400 MHz AJ = 533 MHz AL = 667 MHz
8360
A=revision 2.1 silicon
MPC (rev2.0 silicon only)
1
8360
Blank = Not included E = included
0C TA to 70C TJ
F = 333 MHz G = 400 MHz ZU = TBGA e300 H = 500 MHz core speed VV = TBGA AH = 500 MHz (no lead) AL = 667 MHz
Not all processor, platform, and QUICC Engine frequency combinations are supported. For available frequency combinations, contact your local Freescale Sales Office or authorized distributor. 2 See Section 21, "Package and Pin Listings," for more information on available package types. 3 Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies.
Table 82 shows the SVR settings by device and package type.
Table 82. SVR Settings
Device MPC8360E MPC8360 MPC8358E MPC8358 Package TBGA TBGA TBGA TBGA SVR (Rev 2.0) 0x8048_0020 0x8049_0020 0x804A_0020 0x804B_0020 SVR (Rev 2.1) 0x8048_0021 0x8049_0021 0x804A_0021 0x804B_0021
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Document Number: MPC8360EEC Rev. 2 12/2007

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